Searched refs:SrcReg1 (Results 1 – 6 of 6) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 853 unsigned SrcReg1 = getRegForValue(SrcValue1); in PPCEmitCmp() local 854 if (SrcReg1 == 0) in PPCEmitCmp() 867 auto RC1 = MRI.getRegClass(SrcReg1); in PPCEmitCmp() 889 SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1); in PPCEmitCmp() 935 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp() 937 SrcReg1 = ExtReg; in PPCEmitCmp() 949 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp() 952 .addReg(SrcReg1).addImm(Imm); in PPCEmitCmp() 1301 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local 1302 if (SrcReg1 == 0) return false; in SelectBinaryIntOp() [all …]
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D | PPCInstrInfo.cpp | 4124 Register SrcReg1 = MI.getOperand(1).getReg(); in isSignOrZeroExtended() local 4127 if (!Register::isVirtualRegister(SrcReg1) || in isSignOrZeroExtended() 4131 const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1); in isSignOrZeroExtended()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SIMDInstrOpt.cpp | 432 Register SrcReg1 = MI.getOperand(2).getReg(); in optimizeVectElement() local 452 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement() 456 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg1, LaneNumber, &DupDest)) { in optimizeVectElement() 459 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
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D | AArch64InstrInfo.cpp | 2829 unsigned SrcReg1 = SrcReg; in storeRegPairToStackSlot() local 2833 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot() 2838 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot() 4181 Register SrcReg1 = MUL->getOperand(2).getReg(); in genFusedMultiply() local 4199 if (Register::isVirtualRegister(SrcReg1)) in genFusedMultiply() 4200 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply() 4208 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply() 4214 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply() 4220 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply() 4332 Register SrcReg1 = MUL->getOperand(2).getReg(); in genMaddR() local [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 1425 unsigned SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local 1426 if (SrcReg1 == 0) return false; in ARMEmitCmp() 1436 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp() 1437 if (SrcReg1 == 0) return false; in ARMEmitCmp() 1445 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp() 1449 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp() 1453 .addReg(SrcReg1); in ARMEmitCmp() 1771 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local 1772 if (SrcReg1 == 0) return false; in SelectBinaryIntOp() 1780 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp() [all …]
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/third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
D | radeon_program_alu.c | 64 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) in emit2() argument 75 fpi->U.I.SrcReg[1] = SrcReg1; in emit2() 83 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, in emit3() argument 95 fpi->U.I.SrcReg[1] = SrcReg1; in emit3()
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