| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
243 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
246 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
248 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
257 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
266 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
267 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
317 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
318 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
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| D | ExpandPostRAPseudos.cpp | 86 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
88 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
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| D | TargetRegisterInfo.cpp | 90 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg() argument
91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
111 if (SubIdx) { in printReg()
113 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
115 OS << ":sub(" << SubIdx << ')'; in printReg()
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| D | PeepholeOptimizer.cpp | 460 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
461 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
588 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
591 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1913 if (RegSeqInput.SubIdx == DefSubReg) in getNextSourceFromRegSequence()
1950 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
1969 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none()) in getNextSourceFromInsertSubreg()
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| D | TargetInstrInfo.cpp | 380 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
384 if (!SubIdx) { in getStackSlotRange()
389 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
394 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
411 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
415 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1261 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
1289 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
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| D | RegisterCoalescer.cpp | 288 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
1681 unsigned SubIdx) { in updateRegDefsUses() argument
1718 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue()) in updateRegDefsUses()
1728 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1733 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) { in updateRegDefsUses()
1737 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1750 addUndefFlag(*DstInt, UseIdx, MO, SubIdx); in updateRegDefsUses()
1756 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
2208 const unsigned SubIdx; member in __anon158514010311::JoinVals
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
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| D | MachineOperand.cpp | 75 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
78 if (SubIdx && getSubReg()) in substVirtReg()
79 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
81 if (SubIdx) in substVirtReg()
82 setSubReg(SubIdx); in substVirtReg()
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| D | MachineInstr.cpp | 907 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
909 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
911 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
1140 unsigned SubIdx, in substituteRegister() argument
1143 if (SubIdx) in substituteRegister()
1144 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1154 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
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| D | MachineVerifier.cpp | 1679 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
1682 if (SubIdx) { in visitMachineOperand()
1747 if (SubIdx) { in visitMachineOperand()
1770 if (SubIdx) { in visitMachineOperand()
1772 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
1776 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
1782 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
1789 if (SubIdx) { in visitMachineOperand()
1796 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 338 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
339 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
341 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
348 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
349 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
350 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
516 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
518 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1148 unsigned SubIdx = 0,
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| D | TargetInstrInfo.h | 239 unsigned &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr() argument
340 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
372 unsigned SubIdx, const MachineInstr &Orig,
469 unsigned SubIdx; member
472 unsigned SubIdx = 0)
473 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
113 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
116 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
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| D | ThumbRegisterInfo.h | 41 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
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| D | ARMBaseRegisterInfo.h | 187 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
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| D | ARMBaseInstrInfo.h | 225 unsigned DestReg, unsigned SubIdx,
234 unsigned SubIdx, unsigned State,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 204 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
206 SubIdx = X86::sub_32bit; in getSubRegIndex()
208 SubIdx = X86::sub_16bit; in getSubRegIndex()
210 SubIdx = X86::sub_8bit; in getSubRegIndex()
213 return SubIdx; in getSubRegIndex()
742 unsigned SubIdx; in selectTruncOrPtrToInt() local
745 SubIdx = X86::NoSubRegister; in selectTruncOrPtrToInt()
747 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
749 SubIdx = X86::sub_16bit; in selectTruncOrPtrToInt()
751 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
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| D | X86RegisterInfo.cpp | 101 unsigned SubIdx) const { in getMatchingSuperRegClass()
103 if (!Is64Bit && SubIdx == X86::sub_8bit) { in getMatchingSuperRegClass()
108 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx); in getMatchingSuperRegClass()
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| D | X86InstrInfo.h | 184 unsigned &DstReg, unsigned &SubIdx) const override;
211 unsigned DestReg, unsigned SubIdx,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 449 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
516 SubIdx == DefSubIdx && in EmitSubregNode()
532 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
544 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
546 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
571 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
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| D | InstrEmitter.h | 80 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, MVT VT,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
315 return SubIdx; in getIndexInWord32()
681 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
684 return extractVector(ExVec, SubIdx, dl, ElemTy, MVT::i32, DAG); in extractHvxElementReg()
742 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in insertHvxElementReg() local
745 ValV, SubIdx, dl, ElemTy, DAG); in insertHvxElementReg()
780 unsigned SubIdx; in extractHvxSubvectorReg() local
782 SubIdx = Hexagon::vsub_hi; in extractHvxSubvectorReg()
785 SubIdx = Hexagon::vsub_lo; in extractHvxSubvectorReg()
788 VecV = DAG.getTargetExtractSubreg(SubIdx, dl, VecTy, VecV); in extractHvxSubvectorReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 285 unsigned &SubIdx) const { in isCoalescableExtInstr()
293 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
816 unsigned SubIdx = 0; in insertSelect() local
822 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
826 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
830 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
834 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
838 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
842 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
846 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.h | 82 unsigned SubIdx) const;
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| D | SIInstrInfo.cpp | 715 unsigned SubIdx; in copyPhysReg() local
717 SubIdx = SubIndices[Idx]; in copyPhysReg()
719 SubIdx = SubIndices[SubIndices.size() - Idx - 1]; in copyPhysReg()
722 copyPhysReg(MBB, MI, DL, RI.getSubReg(DestReg, SubIdx), in copyPhysReg()
723 RI.getSubReg(SrcReg, SubIdx), KillSrc); in copyPhysReg()
728 get(Opcode), RI.getSubReg(DestReg, SubIdx)); in copyPhysReg()
730 Builder.addReg(RI.getSubReg(SrcReg, SubIdx)); in copyPhysReg()
2247 unsigned SubIdx = SubIndices[Idx]; in insertSelect() local
2251 .addReg(FalseReg, 0, SubIdx) in insertSelect()
2252 .addReg(TrueReg, 0, SubIdx); in insertSelect()
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