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Searched refs:SubReg (Results 1 – 25 of 66) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsOptionRecord.cpp77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLiveVariables.cpp198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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DPeepholeOptimizer.cpp294 ValueTrackerResult(unsigned Reg, unsigned SubReg) { in ValueTrackerResult() argument
295 addSource(Reg, SubReg); in ValueTrackerResult()
330 return RegSrcs[Idx].SubReg; in getSrcSubReg()
682 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
733 CurSrcPair.SubReg)) in findNextSource()
738 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
764 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
772 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
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DDetectDeadLanes.cpp177 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
178 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
427 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
450 if (SubReg == 0) in determineInitialUsedLanes()
453 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
460 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
461 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
DLiveRangeCalc.cpp86 unsigned SubReg = MO.getSubReg(); in calculate() local
87 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
88 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
177 unsigned SubReg = MO.getSubReg(); in extendToUses() local
178 if (SubReg != 0) { in extendToUses()
179 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
DScheduleDAGInstrs.cpp338 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) { in addPhysRegDeps() local
339 if (Uses.contains(*SubReg)) in addPhysRegDeps()
340 Uses.eraseAll(*SubReg); in addPhysRegDeps()
342 Defs.eraseAll(*SubReg); in addPhysRegDeps()
374 unsigned SubReg = MO.getSubReg(); in getLaneMaskForMO() local
375 if (SubReg == 0) in getLaneMaskForMO()
377 return TRI->getSubRegIndexLaneMask(SubReg); in getLaneMaskForMO()
DMachineInstrBundle.cpp200 unsigned SubReg = *SubRegs; in finalizeBundle() local
201 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
202 LocalDefs.push_back(SubReg); in finalizeBundle()
DLiveIntervals.cpp567 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
568 if (SubReg != 0) { in shrinkToUses()
569 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
1006 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1007 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1418 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1419 if (SubReg != 0 && LaneMask.any() in findLastUseBefore()
1420 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none()) in findLastUseBefore()
1528 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
1529 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
DTailDuplicator.cpp413 if (VI->second.SubReg != 0) { in duplicateInstruction()
415 VI->second.SubReg); in duplicateInstruction()
435 VI->second.SubReg)); in duplicateInstruction()
446 .addReg(VI->second.Reg, 0, VI->second.SubReg); in duplicateInstruction()
992 .addReg(CI.second.Reg, 0, CI.second.SubReg); in appendCopies()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
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DAArch64RegisterInfo.cpp162 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), in UpdateCustomCallPreservedMask() local
164 SubReg.isValid(); ++SubReg) { in UpdateCustomCallPreservedMask()
167 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32); in UpdateCustomCallPreservedMask()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNRegBankReassign.cpp78 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
80 unsigned SubReg; member in __anon25733a380111::GCNRegBankReassign::OperandMask
171 unsigned getRegBankMask(unsigned Reg, unsigned SubReg, int Bank);
198 unsigned getFreeBanks(unsigned Reg, unsigned SubReg, unsigned Mask,
232 Printable printReg(unsigned Reg, unsigned SubReg = 0) const { in printReg() argument
233 return Printable([Reg, SubReg, this](raw_ostream &OS) { in printReg()
243 if (SubReg) in printReg()
244 OS << ':' << TRI->getSubRegIndexName(SubReg); in printReg()
295 unsigned GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, in getRegBankMask() argument
304 if (SubReg) in getRegBankMask()
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DSIShrinkInstructions.cpp390 unsigned Reg, unsigned SubReg, in instAccessReg() argument
401 LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) & in instAccessReg()
411 unsigned Reg, unsigned SubReg, in instReadsReg() argument
413 return instAccessReg(MI->uses(), Reg, SubReg, TRI); in instReadsReg()
417 unsigned Reg, unsigned SubReg, in instModifiesReg() argument
419 return instAccessReg(MI->defs(), Reg, SubReg, TRI); in instModifiesReg()
530 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
531 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
532 .addReg(Y1.Reg, 0, Y1.SubReg) in matchSwap()
533 .addReg(X1.Reg, 0, X1.SubReg).getInstr(); in matchSwap()
DSIFormMemoryClauses.cpp376 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction() argument
378 if (!SubReg) in runOnMachineFunction()
380 B.addDef(R.first, S, SubReg); in runOnMachineFunction()
385 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction() argument
386 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg); in runOnMachineFunction()
DSIPreAllocateWWMRegs.cpp136 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
137 if (SubReg != 0) { in rewriteRegs()
138 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
DSIAddIMGInit.cpp153 Register SubReg = in runOnMachineFunction() local
155 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg) in runOnMachineFunction()
160 .addReg(SubReg) in runOnMachineFunction()
DSIRegisterInfo.cpp687 Register SubReg = NumSubRegs == 1 in buildSpillLoadStore() local
699 auto MIB = spillVGPRtoAGPR(ST, MI, Index, i, SubReg, IsKill); in buildSpillLoadStore()
702 unsigned FinalReg = SubReg; in buildSpillLoadStore()
706 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
707 SubReg = TmpReg; in buildSpillLoadStore()
716 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
787 Register SubReg = in spillSGPR() local
805 .addReg(SubReg, getKillRegState(IsKill)) in spillSGPR()
823 .addReg(SubReg, SubKillState); in spillSGPR()
888 Register SubReg = in restoreSGPR() local
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DR600OptimizeVectorRegisters.cpp211 unsigned SubReg = (*It).first; in RebuildVector() local
218 .addReg(SubReg) in RebuildVector()
220 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td34 class GP8<GPR SubReg, string n> : PPCReg<n> {
35 let HWEncoding = SubReg.HWEncoding;
36 let SubRegs = [SubReg];
41 class SPE<GPR SubReg, string n> : PPCReg<n> {
42 let HWEncoding = SubReg.HWEncoding;
43 let SubRegs = [SubReg];
58 class QFPR<FPR SubReg, string n> : PPCReg<n> {
59 let HWEncoding = SubReg.HWEncoding;
60 let SubRegs = [SubReg];
72 class VR<VF SubReg, string n> : PPCReg<n> {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCRegisterInfo.cpp45 MCRegister SubReg) const { in getSubRegIndex()
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
51 if (*Subs == SubReg) in getSubRegIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h452 unsigned SubReg; member
454 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
455 : Reg(Reg), SubReg(SubReg) {} in Reg()
458 return Reg == P.Reg && SubReg == P.SubReg;
471 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
473 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1843 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1850 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
DMachineInstrBuilder.h89 unsigned SubReg = 0) const {
99 SubReg,
108 unsigned SubReg = 0) const {
109 return addReg(RegNo, Flags | RegState::Define, SubReg);
115 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags, SubReg);
DTargetRegisterInfo.h948 unsigned SubReg, in shouldCoalesce() argument
1002 unsigned SubReg = 0; variable
1022 unsigned getSubReg() const { return SubReg; } in getSubReg()
1033 SubReg = *Idx++;
1034 if (!SubReg)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.cpp533 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
534 Reserved.set(SubReg); in getReservedRegs()
540 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
541 Reserved.set(SubReg); in getReservedRegs()
545 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
546 Reserved.set(SubReg); in getReservedRegs()
559 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
560 Reserved.set(SubReg); in getReservedRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonConstPropagation.cpp86 unsigned Reg, SubReg; member
88 explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {} in RegisterSubReg()
90 : Reg(MO.getReg()), SubReg(MO.getSubReg()) {} in RegisterSubReg()
93 dbgs() << printReg(Reg, TRI, SubReg); in print()
97 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
641 if (DefR.SubReg) { in visitPHI()
674 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC in visitPHI()
1086 if (!R.SubReg) { in getCell()
1938 assert(!DefR.SubReg); in evaluate()
2206 if (!R.SubReg) { in evaluate()
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