| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef() local
198 unsigned SubReg = *SubRegs; in FindLastPartialDef()
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef() local
221 SubRegs.isValid(); ++SubRegs) in FindLastPartialDef()
222 PartDefRegs.insert(*SubRegs); in FindLastPartialDef()
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse()
274 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegUse() local
275 SubRegs.isValid(); ++SubRegs) in HandlePhysRegUse()
276 PhysRegUse[*SubRegs] = &MI; in HandlePhysRegUse()
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| D | CriticalAntiDepBreaker.cpp | 232 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
233 SubRegs.isValid(); ++SubRegs) { in PrescanInstruction()
234 KeepRegs.set(*SubRegs); in PrescanInstruction()
244 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
245 SubRegs.isValid(); ++SubRegs) in PrescanInstruction()
246 KeepRegs.set(*SubRegs); in PrescanInstruction()
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| D | MachineInstrBundle.cpp | 199 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in finalizeBundle() local
200 unsigned SubReg = *SubRegs; in finalizeBundle()
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| D | AggressiveAntiDepBreaker.cpp | 256 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs() local
257 SubRegs.isValid(); ++SubRegs) in GetPassthruRegs()
258 PassthruRegs.insert(*SubRegs); in GetPassthruRegs()
334 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandleLastUse() local
335 unsigned SubregReg = *SubRegs; in HandleLastUse()
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| D | IfConversion.cpp | 1963 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1964 SubRegs.isValid(); ++SubRegs) in IfConvertDiamondCommon()
1965 ExtUses.insert(*SubRegs); in IfConvertDiamondCommon()
1971 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1972 SubRegs.isValid(); ++SubRegs) in IfConvertDiamondCommon()
1973 RedefsByFalse.insert(*SubRegs); in IfConvertDiamondCommon()
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| D | BranchFolding.cpp | 1924 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findHoistingInsertPosAndDeps() local
1925 Uses.erase(*SubRegs); // Use sub-registers to be conservative in findHoistingInsertPosAndDeps()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | LivePhysRegs.h | 82 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg()
83 SubRegs.isValid(); ++SubRegs) in addReg()
84 LiveRegs.insert(*SubRegs); in addReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 36 let SubRegs = [SubReg];
43 let SubRegs = [SubReg];
60 let SubRegs = [SubReg];
75 let SubRegs = [SubReg];
83 let SubRegs = [SubReg];
96 let SubRegs = subregs;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 100 uint32_t SubRegs; // Sub-register set, described above member
284 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
591 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VERegisterInfo.td | 23 let SubRegs = subregs;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 447 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findPotentialNewifiableTFRs() local
448 LastDef[*SubRegs] = &MI; in findPotentialNewifiableTFRs()
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| D | HexagonRegisterInfo.td | 40 let SubRegs = subregs;
61 let SubRegs = subregs;
77 let SubRegs = subregs;
130 let SubRegs = [USR_OVF];
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| D | HexagonFrameLowering.cpp | 251 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) { in getMax32BitSubRegister() local
253 if (*SubRegs > RegNo) in getMax32BitSubRegister()
254 RegNo = *SubRegs; in getMax32BitSubRegister()
256 if (!RegNo || *SubRegs < RegNo) in getMax32BitSubRegister()
257 RegNo = *SubRegs; in getMax32BitSubRegister()
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| D | HexagonInstrInfo.cpp | 2109 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2110 if (RegB == *SubRegs) in isDependent()
2114 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2115 if (RegA == *SubRegs) in isDependent()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 17 let SubRegs = subregs;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 36 let SubRegs = subregs;
45 let SubRegs = subregs;
52 let SubRegs = subregs;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 97 // in the SubRegs field of a Register definition. For example:
143 // SubRegs - A list of registers that are parts of this register. Note these
145 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
147 list<Register> SubRegs = [];
149 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
151 // SubRegs.
188 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
192 let SubRegs = subregs;
359 // SubRegs - N lists of registers to be zipped up. Super-registers are
360 // synthesized from the first element of each SubRegs list, the second
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 874 unsigned SubRegs = 0; in copyPhysReg() local
881 SubRegs = 2; in copyPhysReg()
885 SubRegs = 4; in copyPhysReg()
890 SubRegs = 2; in copyPhysReg()
894 SubRegs = 3; in copyPhysReg()
898 SubRegs = 4; in copyPhysReg()
902 SubRegs = 2; in copyPhysReg()
906 SubRegs = 2; in copyPhysReg()
911 SubRegs = 3; in copyPhysReg()
916 SubRegs = 4; in copyPhysReg()
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| D | ARMRegisterInfo.td | 20 let SubRegs = subregs;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 468 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_EXTRACT() local
472 .addReg(SrcReg, 0, SubRegs[Offset / DstSize]); in selectG_EXTRACT()
503 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
509 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
550 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
554 .addReg(SrcReg, SrcFlags, SubRegs[I]); in selectG_UNMERGE_VALUES()
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| D | SIInstrInfo.cpp | 4225 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR() local
4236 if (SubRegs == 1) { in readlaneVGPRToSGPR()
4244 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
4255 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 24 let SubRegs = subregs;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.td | 30 let SubRegs = [subreg];
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 204 const unsigned SubRegs[]);
1120 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1123 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1129 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1132 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1137 const unsigned SubRegs[]) { in createTuple() argument
1156 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32)); in createTuple()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 18 let SubRegs = subregs;
|