Searched refs:SuccPred (Results 1 – 2 of 2) sorted by relevance
801 for (MachineBasicBlock *SuccPred : Succ->predecessors()) { in isProfitableToTailDup()802 if (SuccPred == Succ || SuccPred == BB in isProfitableToTailDup()803 || BlockToChain[SuccPred] == &Chain in isProfitableToTailDup()804 || (BlockFilter && !BlockFilter->count(SuccPred))) in isProfitableToTailDup()806 auto Freq = MBFI->getBlockFreq(SuccPred) in isProfitableToTailDup()807 * MBPI->getEdgeProbability(SuccPred, Succ); in isProfitableToTailDup()913 for (auto SuccPred : Succ->predecessors()) { in isTrellis() local915 if (Successors.count(SuccPred)) { in isTrellis()917 for (MachineBasicBlock *CheckSucc : SuccPred->successors()) in isTrellis()922 const BlockChain *PredChain = BlockToChain[SuccPred]; in isTrellis()[all …]
2849 for (const SDep &SuccPred : SuccSU->Preds) { in canClobberReachingPhysRegUse() local2850 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()2854 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2855 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()2863 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2864 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()