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Searched refs:TII (Results 1 – 25 of 414) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); in runOnMachineFunction() local
81 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
85 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
89 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
93 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
97 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
101 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
105 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
109 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
113 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPeepholeSDWA.cpp75 const SIInstrInfo *TII; member in __anon751e5d270111::SIPeepholeSDWA
121 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0;
122 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
154 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
155 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
162 uint64_t getSrcMods(const SIInstrInfo *TII,
181 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
182 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
202 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
330 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, in getSrcMods() argument
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DR600ExpandSpecialInstrs.cpp41 const R600InstrInfo *TII = nullptr; member in __anon3d7199360111::R600ExpandSpecialInstrsPass
75 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
78 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
84 TII = ST.getInstrInfo(); in runOnMachineFunction()
86 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
97 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
101 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
104 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
106 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
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DSIShrinkInstructions.cpp71 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates() argument
73 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
116 if (TII->commuteInstruction(MI)) { in foldImmediates()
117 if (foldImmediates(MI, TII, MRI, false)) in foldImmediates()
121 TII->commuteInstruction(MI); in foldImmediates()
128 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand() argument
130 !TII->isInlineConstant(*Src.getParent(), in isKImmOperand()
134 static bool isKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKUImmOperand() argument
136 !TII->isInlineConstant(*Src.getParent(), in isKUImmOperand()
140 static bool isKImmOrKUImmOperand(const SIInstrInfo *TII, in isKImmOrKUImmOperand() argument
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DSIFoldOperands.cpp89 const SIInstrInfo *TII; member in __anon7c461e870111::SIFoldOperands
134 static bool isInlineConstantIfFolded(const SIInstrInfo *TII, in isInlineConstantIfFolded() argument
138 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) in isInlineConstantIfFolded()
159 const MCInstrDesc &MadDesc = TII->get(Opc); in isInlineConstantIfFolded()
160 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType); in isInlineConstantIfFolded()
171 static bool frameIndexMayFold(const SIInstrInfo *TII, in frameIndexMayFold() argument
176 (TII->isMUBUF(UseMI) || TII->isFLATScratch(UseMI)) && in frameIndexMayFold()
185 const SIInstrInfo &TII, in updateOperand() argument
216 switch (TII.get(Opcode).OpInfo[OpNo].OperandType) { in updateOperand()
259 MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32); in updateOperand()
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DGCNHazardRecognizer.cpp45 TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
46 TRI(TII.getRegisterInfo()), in GCNHazardRecognizer()
93 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, in isSendMsgTraceDataOrGDS() argument
95 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
109 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
125 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { in getHWReg() argument
126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
177 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) && in getHazardType()
181 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI) && in getHazardType()
200 static void insertNoopInBundle(MachineInstr *MI, const SIInstrInfo &TII) { in insertNoopInBundle() argument
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DSILoadStoreOptimizer.cpp181 void setMI(MachineBasicBlock::iterator MI, const SIInstrInfo &TII,
202 const SIInstrInfo *TII = nullptr; member in __anon885512d60111::SILoadStoreOptimizer
210 const SIInstrInfo &TII,
280 static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) { in getOpcodeWidth() argument
283 if (TII.isMUBUF(Opc)) { in getOpcodeWidth()
287 if (TII.isMIMG(MI)) { in getOpcodeWidth()
289 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
292 if (TII.isMTBUF(Opc)) { in getOpcodeWidth()
309 static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { in getInstClass() argument
312 if (TII.isMUBUF(Opc)) { in getInstClass()
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DR600Packetizer.cpp57 const R600InstrInfo *TII; member in __anon24f4bbe40111::R600PacketizerList
72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
84 if (TII->isPredicated(*BI)) in getPreviousVector()
86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
94 if (isTrans || TII->isTransOnly(*BI)) { in getPreviousVector()
136 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); in substitutePV()
150 TII(ST.getInstrInfo()), in R600PacketizerList()
151 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
169 if (TII->isVector(MI)) in isSoloInstruction()
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DSIModeRegister.cpp144 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
146 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
148 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
150 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
153 const SIInstrInfo *TII, Status InstrMode);
171 const SIInstrInfo *TII) { in getInstructionMode() argument
172 if (TII->usesFPDPRounding(MI)) { in getInstructionMode()
193 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg() argument
198 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
228 const SIInstrInfo *TII) { in processBlockPhase1() argument
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DGCNDPPCombine.cpp68 const SIInstrInfo *TII; member in __anoned155b830111::GCNDPPCombine
130 return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32; in getDPPOp()
171 OrigMI.getDebugLoc(), TII->get(DPPOp)); in createDPPInst()
174 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
195 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
207 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
209 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
218 if (auto *Mod1 = TII->getNamedOperand(OrigMI, in createDPPInst()
230 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in createDPPInst()
231 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
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DSIAddIMGInit.cpp65 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
78 if (TII->isMIMG(Opcode) && !MI.mayStore()) { in runOnMachineFunction()
79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in runOnMachineFunction()
80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); in runOnMachineFunction()
81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction()
103 TII->getNamedOperand(MI, AMDGPU::OpName::dmask); in runOnMachineFunction()
112 TII->isGather4(Opcode) ? 4 : countPopulation(dmask); in runOnMachineFunction()
127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
133 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
144 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst) in runOnMachineFunction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DPseudoSourceValue.cpp27 PseudoSourceValue::PseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII) in PseudoSourceValue() argument
29 AddressSpace = TII.getAddressSpaceForPseudoSourceKind(Kind); in PseudoSourceValue()
83 unsigned Kind, const TargetInstrInfo &TII) in CallEntryPseudoSourceValue() argument
84 : PseudoSourceValue(Kind, TII) {} in CallEntryPseudoSourceValue()
100 const TargetInstrInfo &TII) in GlobalValuePseudoSourceValue() argument
101 : CallEntryPseudoSourceValue(GlobalValueCallEntry, TII), GV(GV) {} in GlobalValuePseudoSourceValue()
103 const char *ES, const TargetInstrInfo &TII) in ExternalSymbolPseudoSourceValue() argument
104 : CallEntryPseudoSourceValue(ExternalSymbolCallEntry, TII), ES(ES) {} in ExternalSymbolPseudoSourceValue()
108 : TII(TIInfo), in PseudoSourceValueManager()
109 StackPSV(PseudoSourceValue::Stack, TII), in PseudoSourceValueManager()
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DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
98 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { in replaceRetWithPatchableRet()
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
125 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
131 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { in prependRetWithPatchableExit()
134 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp55 const MipsInstrInfo &TII; member in __anon33f400010111::MipsInstructionSelector
77 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), in MipsInstructionSelector()
107 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
146 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
159 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
167 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
169 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
266 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
270 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) in select()
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DMipsBranchExpansion.cpp167 const MipsInstrInfo *TII; member in __anon6d3acf210111::MipsBranchExpansion
299 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); in initMBBInfo()
337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
338 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
387 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
459 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
480 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
485 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
487 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
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DMipsExpandPseudo.cpp38 const MipsInstrInfo *TII; member in __anone423f2ae0111::MipsExpandPseudo
145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
149 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
167 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRFrameLowering.cpp59 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0) in emitPrologue()
87 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
90 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
114 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
131 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
139 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVExpandPseudoInsts.cpp31 const RISCVInstrInfo *TII; member in __anon766288fb0111::RISCVExpandPseudo
78 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
233 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, in doAtomicBinOpExpansion() argument
250 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
256 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
259 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
264 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg) in doAtomicBinOpExpansion()
267 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
273 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, in insertMaskedMerge() argument
284 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in insertMaskedMerge()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreFrameLowering.cpp62 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
72 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
83 const TargetInstrInfo &TII, unsigned DRegNum, in EmitCfiOffset() argument
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
100 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededExtSP() argument
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
123 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
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DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
93 const XCoreInstrInfo &TII, in InsertFPConstInst() argument
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
129 const XCoreInstrInfo &TII, in InsertSPImmInst() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = in emitPrologue() local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
110 const MSP430InstrInfo &TII = in emitEpilogue() local
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); in emitEpilogue()
161 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
191 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in spillCalleeSavedRegisters() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEFrameLowering.cpp41 const VEInstrInfo &TII = in emitPrologueInsns() local
51 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
55 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
59 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
63 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) in emitPrologueInsns()
67 BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX9) in emitPrologueInsns()
79 const VEInstrInfo &TII = in emitEpilogueInsns() local
89 BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX11) in emitEpilogueInsns()
92 BuildMI(MBB, MBBI, dl, TII.get(VE::LDSri), VE::SX16) in emitEpilogueInsns()
95 BuildMI(MBB, MBBI, dl, TII.get(VE::LDSri), VE::SX15) in emitEpilogueInsns()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anonb6c6e90f0111::ARMInstructionSelector
176 : InstructionSelector(), TII(*STI.getInstrInfo()), in ARMInstructionSelector()
213 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
226 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
234 const ARMBaseInstrInfo &TII, in selectMergeValues() argument
238 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP"); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
265 const ARMBaseInstrInfo &TII, in selectUnmergeValues() argument
269 assert(TII.getSubtarget().hasVFP2Base() && in selectUnmergeValues()
290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
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DARMFrameLowering.cpp145 static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII, in isCSRestore() argument
168 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
173 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
176 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
181 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
185 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
252 const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
263 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
280 const TargetInstrInfo &TII, in emitAligningInstructions() argument
303 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
[all …]
DThumb1FrameLowering.cpp69 const TargetInstrInfo &TII, const DebugLoc &dl, in emitPrologueEpilogueSPUpdate() argument
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
97 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
104 const TargetInstrInfo &TII, const DebugLoc &dl, in emitCallSPUpdate() argument
107 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
115 const Thumb1InstrInfo &TII = in eliminateCallFramePseudoInstr() local
125 unsigned Amount = TII.getFrameSize(Old); in eliminateCallFramePseudoInstr()
135 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
138 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
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