| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 64 if (ty == TYPE_F64) in isOpSupported()
115 if (insn->dType == TYPE_F64 || insn->sType == TYPE_F64) in isBarrierRequired()
241 if (insn->dType != TYPE_F64) in getLatency()
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| D | nv50_ir_inlines.h | 68 case TYPE_F64: in typeSizeof()
92 case TYPE_F64: in typeSizeofLog2()
112 case 8: return flt ? TYPE_F64 : (sgn ? TYPE_S64 : TYPE_U64);
124 return (ty >= TYPE_F16 && ty <= TYPE_F64); in isFloatType()
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| D | nv50_ir_emit_nv50.cpp | 587 case TYPE_F64: // fall through in emitLoadStoreSizeLG()
950 if (i->dType == TYPE_F64) { in emitMINMAX()
1305 case TYPE_F64: in emitSET()
1374 case TYPE_F64: in emitCVT()
1376 case TYPE_F64: code[1] = 0xc4404000; break; in emitCVT()
1389 case TYPE_F64: code[1] = 0x8c404000; break; in emitCVT()
1398 case TYPE_F64: code[1] = 0x84404000; break; in emitCVT()
1407 case TYPE_F64: code[1] = 0xc0404000; break; in emitCVT()
1425 case TYPE_F64: code[1] = 0x88404000; break; in emitCVT()
1441 case TYPE_F64: code[1] = 0x80404000; break; in emitCVT()
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| D | nv50_ir_target_nvc0.cpp | 406 case TYPE_F64: in insnCanLoad()
577 if (i->dType == TYPE_F64 || i->sType == TYPE_F64) in getLatency()
669 if (i->dType == TYPE_F64) { in getThroughput()
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| D | nv50_ir_emit_gk110.cpp | 341 if (i->sType == TYPE_F64) { in setShortImmediate()
1020 case TYPE_F64: in emitMINMAX()
1116 case TYPE_F64: op2 = 0x1c0; op1 = 0xb40; break; in emitSET()
1143 case TYPE_F64: op2 = 0x080; op1 = 0x900; break; in emitSET()
2129 case TYPE_F64: in emitLoadStoreType()
2552 if (insn->dType == TYPE_F64) in emitInstruction()
2560 if (insn->dType == TYPE_F64) in emitInstruction()
2569 if (insn->dType == TYPE_F64) in emitInstruction()
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| D | nv50_ir_peephole.cpp | 516 case TYPE_F64: in applyTo()
590 case TYPE_F64: res.data.f64 = a->data.f64 * b->data.f64; break; in expr()
612 case TYPE_F64: res.data.f64 = a->data.f64 / b->data.f64; break; in expr()
622 case TYPE_F64: res.data.f64 = a->data.f64 + b->data.f64; break; in expr()
632 case TYPE_F64: res.data.f64 = a->data.f64 - b->data.f64; break; in expr()
642 case TYPE_F64: res.data.f64 = pow(a->data.f64, b->data.f64); break; in expr()
650 case TYPE_F64: res.data.f64 = MAX2(a->data.f64, b->data.f64); break; in expr()
660 case TYPE_F64: res.data.f64 = MIN2(a->data.f64, b->data.f64); break; in expr()
730 case TYPE_F64: in expr()
830 case TYPE_F64: in expr()
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| D | nv50_ir_target_nv50.cpp | 434 if (ty == TYPE_F64 && chipset < 0xa0) in isOpSupported()
570 if (i->dType == TYPE_F64) { in getThroughput()
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| D | nv50_ir.cpp | 348 reg.type = TYPE_F64; in ImmediateValue()
398 case TYPE_F64: in isInteger()
414 case TYPE_F64: return reg.data.u64 & (1ULL << 63); in isNegative()
452 case TYPE_F64: in applyLog2()
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| D | nv50_ir_target_gv100.cpp | 358 if (i->sType == TYPE_F64) in getOpInfo()
504 if (i->sType == TYPE_F64) { in insnCanLoad()
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| D | nv50_ir_build_util.cpp | 424 return mkOp1v(OP_MOV, TYPE_F64, dst ? dst : getScratch(8), mkImm(d)); in loadImm()
600 case TYPE_F64: in split64BitOpPostRA()
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| D | nv50_ir_emit_gm107.cpp | 350 } else if (insn->sType == TYPE_F64) { in emitIMMD()
3508 if (insn->dType == TYPE_F64) in emitInstruction()
3518 if (insn->dType == TYPE_F64) in emitInstruction()
3529 if (insn->dType == TYPE_F64) in emitInstruction()
3546 if (insn->dType == TYPE_F64) in emitInstruction()
3593 if (insn->sType == TYPE_F64) in emitInstruction()
3601 if (insn->sType == TYPE_F64) in emitInstruction()
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| D | nv50_ir_from_tgsi.cpp | 602 return nv50_ir::TYPE_F64; in inferSrcType()
671 return nv50_ir::TYPE_F64; in inferDstType()
4033 mkOp1(OP_FLOOR, TYPE_F64, dst, src0); in handleInstruction()
4034 mkOp2(OP_SUB, TYPE_F64, dst, src0, dst); in handleInstruction()
4156 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0) in handleInstruction()
4174 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero); in handleInstruction()
4175 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero); in handleInstruction()
4177 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32); in handleInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 1037 if (i->dType == TYPE_F64) in emitMINMAX()
1172 if (i->sType == TYPE_F64) in emitSET()
1819 case TYPE_F64: in emitLoadStoreType()
2728 if (insn->dType == TYPE_F64) in emitInstruction()
2736 if (insn->dType == TYPE_F64) in emitInstruction()
2745 if (insn->dType == TYPE_F64) in emitInstruction()
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| D | nv50_ir_emit_gv100.h | 310 if (insn->sType == TYPE_F64) { in emitIMMD()
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| D | nv50_ir_lowering_gv100.cpp | 465 if (i->dType == TYPE_F64) in visit()
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| D | nv50_ir_print.cpp | 522 case TYPE_F64: PRINT("%f", reg.data.f64); break; in print()
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| D | nv50_ir_lowering_nvc0.cpp | 121 assert(i->dType == TYPE_F64); in handleRCPRSQ()
346 if (i->dType == TYPE_F64) in visit()
362 if (typeSizeof(i->sType) == 8 && i->sType != TYPE_F64) in visit()
3140 if (i->dType == TYPE_F64) { in handleSQRT()
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| D | nv50_ir.h | 325 TYPE_F64, enumerator
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| D | nv50_ir_emit_gv100.cpp | 1969 if (insn->sType == TYPE_F64) in emitInstruction()
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| D | nv50_ir_from_nir.cpp | 2724 if (dType == TYPE_F64) { in visit()
2726 mkCvt(OP_CVT, TYPE_F64, newDefs[0], iType, val0); in visit()
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