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Searched refs:TmpReg (Results 1 – 25 of 33) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SpeculationHardening.cpp161 unsigned TmpReg) const;
307 unsigned TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local
309 << ((TmpReg == 0) ? "no register " : "register "); in instrumentControlFlow()
310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow()
312 if (TmpReg == 0) in instrumentControlFlow()
315 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
317 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
384 unsigned TmpReg) const { in insertRegToSPTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
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DAArch64FastISel.cpp423 unsigned TmpReg = createResultReg(RC); in materializeFP() local
424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
430 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
4180 Register TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
4182 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4186 Op0 = TmpReg; in emitLSL_ri()
4301 Register TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4303 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4307 Op0 = TmpReg; in emitLSR_ri()
4410 Register TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2700 unsigned TmpReg = DstReg; in loadImmediate() local
2708 TmpReg = ATReg; in loadImmediate()
2728 unsigned TmpReg = DstReg; in loadImmediate() local
2730 TmpReg = getATReg(IDLoc); in loadImmediate()
2731 if (!TmpReg) in loadImmediate()
2735 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2737 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2750 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2751 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2753 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp157 unsigned TmpReg = createResultReg(ToRC); in copyRegToRegClass() local
159 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass()
160 return TmpReg; in copyRegToRegClass()
1024 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
1025 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg()
1027 SrcReg = TmpReg; in PPCMoveToFPReg()
1119 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1120 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP()
1123 SrcReg = TmpReg; in SelectIToFP()
1445 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
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DPPCFrameLowering.cpp2318 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
2331 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr()
2333 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr()
2334 .addReg(TmpReg, RegState::Kill) in eliminateCallFramePseudoInstr()
2338 .addReg(TmpReg); in eliminateCallFramePseudoInstr()
DPPCMIPeephole.cpp669 Register TmpReg = in simplifyCode() local
672 TmpReg); in simplifyCode()
675 .addReg(TmpReg) in simplifyCode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp584 unsigned TmpReg = 0; // 0 for no temporary register in expand() local
593 TmpReg = scavengeGPR8(MI); in expand()
595 unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand()
596 unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expand()
604 if (TmpReg) in expand()
605 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
613 if (TmpReg) { in expand()
615 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg); in expand()
695 unsigned TmpReg = 0; // 0 for no temporary register in expand() local
709 TmpReg = scavengeGPR8(MI); in expand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp299 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
302 TmpReg) in foldVGPRCopyIntoRegSequence()
312 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence()
313 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence()
316 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
623 Register TmpReg in runOnMachineFunction() local
627 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in runOnMachineFunction()
629 MI.getOperand(1).setReg(TmpReg); in runOnMachineFunction()
DSIRegisterInfo.cpp646 Register TmpReg = in buildSpillLoadStore() local
703 if (TmpReg != AMDGPU::NoRegister) { in buildSpillLoadStore()
705 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_READ_B32), TmpReg) in buildSpillLoadStore()
707 SubReg = TmpReg; in buildSpillLoadStore()
727 if (!IsStore && TmpReg != AMDGPU::NoRegister) in buildSpillLoadStore()
730 .addReg(TmpReg, RegState::Kill); in buildSpillLoadStore()
1218 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex() local
1219 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1221 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DSILowerI1Copies.cpp704 unsigned TmpReg = createLaneMaskReg(*MF); in lowerCopiesToI1() local
705 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg) in lowerCopiesToI1()
708 MI.getOperand(1).setReg(TmpReg); in lowerCopiesToI1()
709 SrcReg = TmpReg; in lowerCopiesToI1()
DSIInstrInfo.cpp1238 MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, in calculateLDSSpillAddress() argument
1324 getAddNoCarry(MBB, MI, DL, TmpReg) in calculateLDSSpillAddress()
1329 return TmpReg; in calculateLDSSpillAddress()
5154 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
5160 BuildMI(MBB, MII, DL, get(SubOp), TmpReg) in lowerScalarAbs()
5166 .addReg(TmpReg); in lowerScalarAbs()
5608 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local
5611 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE()
5618 .addReg(TmpReg) in splitScalar64BitBFE()
5673 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp287 Register TmpReg = in ExpandFPMLxInstruction() local
290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DThumbRegisterInfo.cpp513 Register TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
517 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
520 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
524 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
529 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DThumb1FrameLowering.cpp583 unsigned &TmpReg) { in findTemporariesForLR() argument
584 PopReg = TmpReg = 0; in findTemporariesForLR()
590 TmpReg = 0; in findTemporariesForLR()
595 TmpReg = Reg; in findTemporariesForLR()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1908 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local
1912 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg) in mergePredStateIntoSP()
1919 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP()
1929 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local
1934 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP()
1938 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP()
2036 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local
2071 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr()
2102 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr()
2115 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg) in hardenLoadAddr()
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DX86CmovConversion.cpp758 Register TmpReg = MRI->createVirtualRegister(RC); in convertCmovInstsToBranches() local
761 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, in convertCmovInstsToBranches()
803 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg; in convertCmovInstsToBranches()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h649 Register TmpReg; in lookThroughCopyInstrs() local
650 while (mi_match(Reg, MRI, m_Copy(m_Reg(TmpReg)))) { in lookThroughCopyInstrs()
651 if (MRI.getType(TmpReg).isValid()) in lookThroughCopyInstrs()
652 Reg = TmpReg; in lookThroughCopyInstrs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFMISimplifyPatchable.cpp164 Register TmpReg = I->getParent()->getOperand(0).getReg(); in processCandidate() local
165 processDstReg(MRI, TmpReg, DstReg, GVal, false); in processCandidate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp336 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument
359 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
361 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
363 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp801 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
803 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO); in narrowScalar()
804 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
817 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
820 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
825 .addDef(TmpReg) in narrowScalar()
831 MIRBuilder.buildZExt(DstReg, TmpReg); in narrowScalar()
833 MIRBuilder.buildSExt(DstReg, TmpReg); in narrowScalar()
853 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
855 MIRBuilder.buildTrunc(TmpReg, SrcReg); in narrowScalar()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp93 void emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
1663 void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg, in emitAuipcInstPair() argument
1679 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
1687 .addOperand(TmpReg) in emitAuipcInstPair()
1773 MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); in emitLoadStoreSymbol() local
1775 emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI, in emitLoadStoreSymbol()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp749 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
758 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
763 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
764 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
DMipsTargetStreamer.h160 int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anonc3356ce30111::X86AsmParser::IntelExprStateMachine
369 TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0), in IntelExprStateMachine()
480 BaseReg = TmpReg; in onPlus()
486 IndexReg = TmpReg; in onPlus()
535 BaseReg = TmpReg; in onMinus()
541 IndexReg = TmpReg; in onMinus()
586 TmpReg = Reg; in onRegister()
670 IndexReg = TmpReg; in onInteger()
764 BaseReg = TmpReg; in onRBrac()
767 IndexReg = TmpReg; in onRBrac()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp366 unsigned TmpReg = FromReg; in isRevCopyChain() local
368 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); in isRevCopyChain()
372 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
374 if (TmpReg == ToReg) in isRevCopyChain()

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