Searched refs:VECREDUCE_SMIN (Results 1 – 14 of 14) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 480 case ISD::VECREDUCE_SMIN: in LegalizeOp()
984 case ISD::VECREDUCE_SMIN: in Expand()
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| D | SelectionDAGDumper.cpp | 446 case ISD::VECREDUCE_SMIN: return "vecreduce_smin"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 612 case ISD::VECREDUCE_SMIN: in ScalarizeVectorOperand()
1992 case ISD::VECREDUCE_SMIN: in SplitVectorOperand()
2078 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break; in SplitVecOp_VECREDUCE()
4233 case ISD::VECREDUCE_SMIN: in WidenVectorOperand()
4707 case ISD::VECREDUCE_SMIN: in WidenVecOp_VECREDUCE()
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| D | LegalizeIntegerTypes.cpp | 196 case ISD::VECREDUCE_SMIN: in PromoteIntegerResult()
1319 case ISD::VECREDUCE_SMIN: in PromoteIntegerOperand()
1744 case ISD::VECREDUCE_SMIN: in PromoteIntOp_VECREDUCE()
1925 case ISD::VECREDUCE_SMIN: in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 1156 case ISD::VECREDUCE_SMIN: in LegalizeOp()
3805 case ISD::VECREDUCE_SMIN: in ExpandNode()
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| D | TargetLowering.cpp | 7619 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break; in expandVecReduce()
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| D | SelectionDAGBuilder.cpp | 8999 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); in visitVectorReduce()
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| D | DAGCombiner.cpp | 1621 case ISD::VECREDUCE_SMIN: in visit()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 720 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); in initActions()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 430 def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 785 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
3270 case ISD::VECREDUCE_SMIN: in LowerOperation()
8551 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
12934 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 293 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal); in addMVEVectorTypes()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenDAGISel.inc | 50944 /*110287*/ /*SwitchOpcode*/ 13|128,1/*141*/, TARGET_VAL(ISD::VECREDUCE_SMIN),// ->110432
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