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Searched refs:VLIW (Results 1 – 7 of 7) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600Schedule.td9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/
DCREDITS.TXT99 D: Deterministic finite automaton based infrastructure for VLIW packetization
238 D: Implemented DFA-based target independent VLIW packetizer
284 D: Backend for Qualcomm's Hexagon VLIW processor.
/third_party/mesa3d/docs/relnotes/
D18.1.0.rst72 - [R600] Miscompilation of TGSI to VLIW causes artifacts in Gallium
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dnotes.markdown377 - **post\_scheduler** - ALU scheduler, handles VLIW packing and
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetLowering.h104 VLIW // Scheduling for VLIW targets. enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp270 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1303 setSchedulingPreference(Sched::VLIW); in HexagonTargetLowering()