/third_party/node/deps/v8/src/codegen/x64/ |
D | fma-instr.h | 23 V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \ 24 V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \ 25 V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \ 26 V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \ 27 V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \ 28 V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \ 29 V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \ 30 V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \ 31 V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \ 32 V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \ [all …]
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/third_party/node/deps/v8/src/codegen/ia32/ |
D | fma-instr.h | 23 V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \ 24 V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \ 25 V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \ 26 V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \ 27 V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \ 28 V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \ 29 V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \ 30 V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \ 31 V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \ 32 V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \ [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonBitTracker.cpp | 313 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate() local 325 return rr0(eIMM(im(1), W0), Outputs); in evaluate() 327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate() 329 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate() 335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() 347 uint16_t RW = W0; in evaluate() 356 uint16_t RW = W0; in evaluate() 372 assert(W0 == 64 && W1 == 32); in evaluate() 373 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1)); in evaluate() 381 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs); in evaluate() [all …]
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D | HexagonVectorPrint.cpp | 75 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg() 185 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction() 186 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); in runOnMachineFunction() 187 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction() 189 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
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D | HexagonCallingConv.td | 89 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>, 103 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>, 121 CCAssignToReg<[W0]>>>, 129 CCAssignToReg<[W0]>>>,
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D | HexagonISelLoweringHVX.cpp | 553 SDValue W0 = isUndef(PredV) in createHvxPrefixPred() local 556 Words[IdxW].push_back(Hi32(W0)); in createHvxPrefixPred() 557 Words[IdxW].push_back(Lo32(W0)); in createHvxPrefixPred() 802 SDValue W0 = extractHvxElementReg(WordVec, W0Idx, dl, MVT::i32, DAG); in extractHvxSubvectorReg() local 804 return DAG.getBitcast(ResTy, W0); in extractHvxSubvectorReg() 808 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); in extractHvxSubvectorReg() 868 SDValue W0 = DAG.getNode(HexagonISD::VEXTRACTW, dl, MVT::i32, {ShuffV, Zero}); in extractHvxSubvectorPred() local 871 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred()
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/third_party/node/deps/openssl/openssl/crypto/sha/asm/ |
D | sha512-armv8.pl | 364 my ($W0,$W1)=("v16.4s","v17.4s"); 382 ld1.32 {$W0},[$Ktbl],#16 393 add.i32 $W0,$W0,@MSG[0] 396 sha256h $ABCD,$EFGH,$W0 397 sha256h2 $EFGH,$abcd,$W0 400 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG)); 404 add.i32 $W0,$W0,@MSG[0] 406 sha256h $ABCD,$EFGH,$W0 407 sha256h2 $EFGH,$abcd,$W0 409 ld1.32 {$W0},[$Ktbl],#16 [all …]
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D | sha256-armv4.pl | 608 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15)); 634 vld1.32 {$W0},[$Ktbl]! 646 vadd.i32 $W0,$W0,@MSG[0] 649 sha256h $ABCD,$EFGH,$W0 650 sha256h2 $EFGH,$abcd,$W0 653 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG)); 657 vadd.i32 $W0,$W0,@MSG[0] 659 sha256h $ABCD,$EFGH,$W0 660 sha256h2 $EFGH,$abcd,$W0 662 vld1.32 {$W0},[$Ktbl]! [all …]
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D | sha1-armv8.pl | 248 my ($W0,$W1)=("v20.4s","v21.4s"); 272 add.i32 $W0,@Kxx[0],@MSG[0] 279 sha1c $ABCD,$E,$W0 // 0 280 add.i32 $W0,@Kxx[$j],@MSG[2] 294 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 303 sha1p $ABCD,$E0,$W0
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D | sha1-armv4-large.pl | 624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14)); 658 vadd.i32 $W0,@Kxx[0],@MSG[0] 666 sha1c $ABCD,$E,$W0 667 vadd.i32 $W0,@Kxx[$j],@MSG[2] 681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 690 sha1p $ABCD,$E0,$W0
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/third_party/openssl/crypto/sha/asm/ |
D | sha512-armv8.pl | 364 my ($W0,$W1)=("v16.4s","v17.4s"); 382 ld1.32 {$W0},[$Ktbl],#16 393 add.i32 $W0,$W0,@MSG[0] 396 sha256h $ABCD,$EFGH,$W0 397 sha256h2 $EFGH,$abcd,$W0 400 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG)); 404 add.i32 $W0,$W0,@MSG[0] 406 sha256h $ABCD,$EFGH,$W0 407 sha256h2 $EFGH,$abcd,$W0 409 ld1.32 {$W0},[$Ktbl],#16 [all …]
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D | sha256-armv4.pl | 608 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15)); 634 vld1.32 {$W0},[$Ktbl]! 646 vadd.i32 $W0,$W0,@MSG[0] 649 sha256h $ABCD,$EFGH,$W0 650 sha256h2 $EFGH,$abcd,$W0 653 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG)); 657 vadd.i32 $W0,$W0,@MSG[0] 659 sha256h $ABCD,$EFGH,$W0 660 sha256h2 $EFGH,$abcd,$W0 662 vld1.32 {$W0},[$Ktbl]! [all …]
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D | sha1-armv8.pl | 248 my ($W0,$W1)=("v20.4s","v21.4s"); 272 add.i32 $W0,@Kxx[0],@MSG[0] 279 sha1c $ABCD,$E,$W0 // 0 280 add.i32 $W0,@Kxx[$j],@MSG[2] 294 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 303 sha1p $ABCD,$E0,$W0
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D | sha1-armv4-large.pl | 624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14)); 658 vadd.i32 $W0,@Kxx[0],@MSG[0] 666 sha1c $ABCD,$E,$W0 667 vadd.i32 $W0,@Kxx[$j],@MSG[2] 681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 690 sha1p $ABCD,$E0,$W0
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/third_party/ffmpeg/libavcodec/mips/ |
D | wmv2dsp_mmi.c | 28 #define W0 2048 macro 43 a0 = W0 * b[0] + W0 * b[4]; in wmv2_idct_row_mmi() 47 a4 = W0 * b[0] - W0 * b[4]; in wmv2_idct_row_mmi() 73 a0 = (W0 * b[ 0] + W0 * b[32] ) >> 3; in wmv2_idct_col_mmi() 77 a4 = (W0 * b[ 0] - W0 * b[32] ) >> 3; in wmv2_idct_col_mmi()
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/third_party/ffmpeg/libavcodec/ |
D | wmv2dsp.c | 27 #define W0 2048 macro 48 a0 = W0 * b[0] + W0 * b[4]; in wmv2_idct_row() 49 a4 = W0 * b[0] - W0 * b[4]; in wmv2_idct_row() 78 a0 = (W0 * b[8 * 0] + W0 * b[8 * 4] ) >> 3; in wmv2_idct_col() 79 a4 = (W0 * b[8 * 0] - W0 * b[8 * 4] ) >> 3; in wmv2_idct_col()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64CallingConvention.td | 56 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1], [W0, W1]>>>>>, 92 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 102 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 141 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 144 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 209 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], 214 [W0, W1, W2, W3, W4, W5, W6]>>>, 219 [W0, W1, W2, W3, W4, W5, W6, W7]>>, 298 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0). 300 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>, [all …]
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D | AArch64CollectLOH.cpp | 262 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex() 265 if (AArch64::W0 <= Reg && Reg <= AArch64::W30) in mapRegToGPRIndex() 266 return Reg - AArch64::W0; in mapRegToGPRIndex()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
D | BPFCallingConv.td | 30 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [R0]>>, 31 CCIfType<[i64], CCAssignToRegWithShadow<[R0], [W0]>>
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D | BPFRegisterInfo.td | 41 W0, // Return value
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/third_party/node/deps/openssl/openssl/crypto/sm3/ |
D | sm3_local.h | 51 #define EXPAND(W0,W7,W13,W3,W10) \ argument 52 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
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/third_party/openssl/crypto/sm3/ |
D | sm3_local.h | 51 #define EXPAND(W0,W7,W13,W3,W10) \ argument 52 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
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/third_party/mesa3d/src/intel/isl/ |
D | isl.c | 1290 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_slice0_extent_sa_gfx4_2d() local 1294 uint32_t W = isl_minify(W0, l); in isl_calc_phys_slice0_extent_sa_gfx4_2d() 1398 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx4_3d() local 1404 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); in isl_calc_phys_total_extent_el_gfx4_3d() 1453 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx6_stencil_hiz() local 1466 const uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gfx6_stencil_hiz() 1513 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx9_1d() local 1516 uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gfx9_1d() 2524 const uint32_t W0 = surf->phys_level0_sa.width; in get_image_offset_sa_gfx4_2d() local 2535 uint32_t W = isl_minify(W0, l); in get_image_offset_sa_gfx4_2d() [all …]
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/third_party/vk-gl-cts/framework/delibs/cmake/ |
D | CFlags.cmake | 77 set(DE_3RD_PARTY_C_FLAGS "${CMAKE_C_FLAGS} ${MSC_BASE_FLAGS} /W0") 78 set(DE_3RD_PARTY_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${MSC_BASE_FLAGS} /EHsc /W0")
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenCallingConv.inc | 93 AArch64::W0, AArch64::W1 216 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64… 258 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64… 460 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64… 477 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6 502 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64… 915 if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) { 922 if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) { 1055 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64… 1071 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64… [all …]
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