1 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2010-2022 Hans Petter Selasky 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _XHCI_H_ 30 #define _XHCI_H_ 31 32 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 33 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 34 #define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */ 35 #define XHCI_MAX_EVENTS (16 * 13) 36 #define XHCI_MAX_COMMANDS (16 * 1) 37 #define XHCI_MAX_RSEG 1 38 #define XHCI_MAX_TRANSFERS 4 39 #if USB_MAX_EP_STREAMS == 8 40 #define XHCI_MAX_STREAMS 8 41 #define XHCI_MAX_STREAMS_LOG 3 42 #elif USB_MAX_EP_STREAMS == 1 43 #define XHCI_MAX_STREAMS 1 44 #define XHCI_MAX_STREAMS_LOG 0 45 #else 46 #error "The USB_MAX_EP_STREAMS value is not supported." 47 #endif 48 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 49 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 50 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 51 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 52 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 53 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 54 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 55 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 56 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 57 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 58 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 59 #define XHCI_TRB_ALIGN 16 /* bytes */ 60 #define XHCI_TD_ALIGN 64 /* bytes */ 61 #define XHCI_PAGE_SIZE 4096 /* bytes */ 62 63 struct xhci_dev_ctx_addr { 64 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 65 struct { 66 volatile uint64_t dummy; 67 } __aligned(64) padding; 68 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 69 }; 70 71 #define XHCI_EPNO2EPID(x) \ 72 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 73 74 struct xhci_slot_ctx { 75 volatile uint32_t dwSctx0; 76 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 77 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 78 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 79 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 80 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 81 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 82 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 83 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 84 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 85 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 86 volatile uint32_t dwSctx1; 87 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 88 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 89 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 90 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 91 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 92 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 93 volatile uint32_t dwSctx2; 94 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 95 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 96 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 97 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 98 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 99 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 100 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 101 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 102 volatile uint32_t dwSctx3; 103 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 104 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 105 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 106 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 107 volatile uint32_t dwSctx4; 108 volatile uint32_t dwSctx5; 109 volatile uint32_t dwSctx6; 110 volatile uint32_t dwSctx7; 111 }; 112 113 struct xhci_endp_ctx { 114 volatile uint32_t dwEpCtx0; 115 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 116 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 117 #define XHCI_EPCTX_0_EPSTATE_DISABLED 0 118 #define XHCI_EPCTX_0_EPSTATE_RUNNING 1 119 #define XHCI_EPCTX_0_EPSTATE_HALTED 2 120 #define XHCI_EPCTX_0_EPSTATE_STOPPED 3 121 #define XHCI_EPCTX_0_EPSTATE_ERROR 4 122 #define XHCI_EPCTX_0_EPSTATE_RESERVED_5 5 123 #define XHCI_EPCTX_0_EPSTATE_RESERVED_6 6 124 #define XHCI_EPCTX_0_EPSTATE_RESERVED_7 7 125 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 126 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 127 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 128 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 129 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 130 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 131 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 132 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 133 volatile uint32_t dwEpCtx1; 134 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 135 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 136 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 137 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 138 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 139 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 140 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 141 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 142 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 143 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 144 volatile uint64_t qwEpCtx2; 145 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 146 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 147 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 148 volatile uint32_t dwEpCtx4; 149 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 150 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 151 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 152 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 153 volatile uint32_t dwEpCtx5; 154 volatile uint32_t dwEpCtx6; 155 volatile uint32_t dwEpCtx7; 156 }; 157 158 struct xhci_input_ctx { 159 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 160 volatile uint32_t dwInCtx0; 161 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 162 volatile uint32_t dwInCtx1; 163 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 164 volatile uint32_t dwInCtx2; 165 volatile uint32_t dwInCtx3; 166 volatile uint32_t dwInCtx4; 167 volatile uint32_t dwInCtx5; 168 volatile uint32_t dwInCtx6; 169 volatile uint32_t dwInCtx7; 170 }; 171 172 struct xhci_input_dev_ctx { 173 struct xhci_input_ctx ctx_input; 174 struct xhci_slot_ctx ctx_slot; 175 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 176 }; 177 178 struct xhci_dev_ctx { 179 struct xhci_slot_ctx ctx_slot; 180 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 181 } __aligned(XHCI_DEV_CTX_ALIGN); 182 183 struct xhci_stream_ctx { 184 volatile uint64_t qwSctx0; 185 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 186 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 187 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 188 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 189 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 190 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 191 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 192 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 193 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 194 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 195 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 196 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 197 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 198 volatile uint32_t dwSctx2; 199 volatile uint32_t dwSctx3; 200 }; 201 202 struct xhci_trb { 203 volatile uint64_t qwTrb0; 204 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 205 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 206 volatile uint32_t dwTrb2; 207 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 208 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 209 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 210 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 211 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 212 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 213 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 214 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 215 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 216 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 217 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 218 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 219 220 volatile uint32_t dwTrb3; 221 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 222 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 223 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 224 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 225 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 226 #define XHCI_TRB_3_ISP_BIT (1U << 2) 227 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 228 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 229 #define XHCI_TRB_3_IOC_BIT (1U << 5) 230 #define XHCI_TRB_3_IDT_BIT (1U << 6) 231 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 232 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 233 #define XHCI_TRB_3_BEI_BIT (1U << 9) 234 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 235 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 236 #define XHCI_TRB_3_BSR_BIT (1U << 9) 237 #define XHCI_TRB_3_TRT_MASK (3U << 16) 238 #define XHCI_TRB_3_TRT_NONE (0U << 16) 239 #define XHCI_TRB_3_TRT_OUT (2U << 16) 240 #define XHCI_TRB_3_TRT_IN (3U << 16) 241 #define XHCI_TRB_3_DIR_IN (1U << 16) 242 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 243 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 244 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 245 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 246 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 247 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 248 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 249 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 250 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 251 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 252 253 /* Commands */ 254 #define XHCI_TRB_TYPE_RESERVED 0x00 255 #define XHCI_TRB_TYPE_NORMAL 0x01 256 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 257 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 258 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 259 #define XHCI_TRB_TYPE_ISOCH 0x05 260 #define XHCI_TRB_TYPE_LINK 0x06 261 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 262 #define XHCI_TRB_TYPE_NOOP 0x08 263 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 264 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 265 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 266 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 267 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 268 #define XHCI_TRB_TYPE_RESET_EP 0x0E 269 #define XHCI_TRB_TYPE_STOP_EP 0x0F 270 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 271 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 272 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 273 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 274 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 275 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 276 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 277 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 278 279 /* Events */ 280 #define XHCI_TRB_EVENT_TRANSFER 0x20 281 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 282 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 283 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 284 #define XHCI_TRB_EVENT_DOORBELL 0x24 285 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 286 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 287 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 288 289 /* Error codes */ 290 #define XHCI_TRB_ERROR_INVALID 0x00 291 #define XHCI_TRB_ERROR_SUCCESS 0x01 292 #define XHCI_TRB_ERROR_DATA_BUF 0x02 293 #define XHCI_TRB_ERROR_BABBLE 0x03 294 #define XHCI_TRB_ERROR_XACT 0x04 295 #define XHCI_TRB_ERROR_TRB 0x05 296 #define XHCI_TRB_ERROR_STALL 0x06 297 #define XHCI_TRB_ERROR_RESOURCE 0x07 298 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 299 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 300 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 301 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 302 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 303 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 304 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 305 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 306 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 307 #define XHCI_TRB_ERROR_PARAMETER 0x11 308 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 309 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 310 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 311 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 312 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 313 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 314 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 315 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 316 #define XHCI_TRB_ERROR_STOPPED 0x1A 317 #define XHCI_TRB_ERROR_LENGTH 0x1B 318 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 319 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 320 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 321 #define XHCI_TRB_ERROR_UNDEFINED 0x21 322 #define XHCI_TRB_ERROR_INVALID_SID 0x22 323 #define XHCI_TRB_ERROR_SEC_BW 0x23 324 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 325 } __aligned(4); 326 327 struct xhci_dev_endpoint_trbs { 328 struct xhci_trb trb[(XHCI_MAX_STREAMS * 329 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 330 }; 331 332 #if (USB_PAGE_SIZE < 4096) 333 #error "The XHCI driver needs a pagesize above or equal to 4K" 334 #endif 335 336 /* Define the maximum payload which we will handle in a single TRB */ 337 #define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */ 338 339 /* Define the maximum payload of a single scatter-gather list element */ 340 #define XHCI_TD_PAGE_SIZE \ 341 ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX) 342 343 /* Define the maximum length of the scatter-gather list */ 344 #define XHCI_TD_PAGE_NBUF \ 345 (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1) 346 347 struct xhci_td { 348 /* one LINK TRB has been added to the TRB array */ 349 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 350 351 /* 352 * Extra information needed: 353 */ 354 uint64_t td_self; 355 struct xhci_td *next; 356 struct xhci_td *alt_next; 357 struct xhci_td *obj_next; 358 struct usb_page_cache *page_cache; 359 uint32_t len; 360 uint32_t remainder; 361 uint8_t ntrb; 362 uint8_t status; 363 } __aligned(XHCI_TRB_ALIGN); 364 365 struct xhci_command { 366 struct xhci_trb trb; 367 TAILQ_ENTRY(xhci_command) entry; 368 }; 369 370 struct xhci_event_ring_seg { 371 volatile uint64_t qwEvrsTablePtr; 372 volatile uint32_t dwEvrsTableSize; 373 volatile uint32_t dwEvrsReserved; 374 }; 375 376 struct xhci_hw_root { 377 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 378 struct { 379 volatile uint64_t dummy; 380 } __aligned(64) padding; 381 struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 382 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 383 }; 384 385 struct xhci_endpoint_ext { 386 struct xhci_trb *trb; 387 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; 388 struct usb_page_cache *page_cache; 389 uint64_t physaddr; 390 uint8_t trb_used[XHCI_MAX_STREAMS]; 391 uint8_t trb_index[XHCI_MAX_STREAMS]; 392 uint8_t trb_halted; 393 uint8_t trb_running; 394 uint8_t trb_ep_mode; 395 uint8_t trb_ep_maxp; 396 }; 397 398 enum { 399 XHCI_ST_DISABLED, 400 XHCI_ST_ENABLED, 401 XHCI_ST_DEFAULT, 402 XHCI_ST_ADDRESSED, 403 XHCI_ST_CONFIGURED, 404 XHCI_ST_MAX 405 }; 406 407 struct xhci_hw_dev { 408 struct usb_page_cache device_pc; 409 struct usb_page_cache input_pc; 410 struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; 411 412 struct usb_page device_pg; 413 struct usb_page input_pg; 414 struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; 415 416 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 417 418 uint32_t ep_configured; 419 420 uint8_t state; 421 uint8_t nports; 422 uint8_t tt; 423 uint8_t context_num; 424 }; 425 426 struct xhci_hw_softc { 427 struct usb_page_cache root_pc; 428 struct usb_page_cache ctx_pc; 429 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 430 431 struct usb_page root_pg; 432 struct usb_page ctx_pg; 433 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 434 435 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 436 }; 437 438 struct xhci_config_desc { 439 struct usb_config_descriptor confd; 440 struct usb_interface_descriptor ifcd; 441 struct usb_endpoint_descriptor endpd; 442 struct usb_endpoint_ss_comp_descriptor endpcd; 443 } __packed; 444 445 struct xhci_bos_desc { 446 struct usb_bos_descriptor bosd; 447 struct usb_devcap_usb2ext_descriptor usb2extd; 448 struct usb_devcap_ss_descriptor usbdcd; 449 struct usb_devcap_container_id_descriptor cidd; 450 } __packed; 451 452 union xhci_hub_desc { 453 struct usb_status stat; 454 struct usb_port_status ps; 455 struct usb_hub_ss_descriptor hubd; 456 uint8_t temp[128]; 457 }; 458 459 typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); 460 461 struct xhci_softc { 462 struct xhci_hw_softc sc_hw; 463 /* base device */ 464 struct usb_bus sc_bus; 465 /* configure message */ 466 struct usb_bus_msg sc_config_msg[2]; 467 468 struct usb_callout sc_callout; 469 470 xhci_port_route_t *sc_port_route; 471 472 union xhci_hub_desc sc_hub_desc; 473 474 struct cv sc_cmd_cv; 475 struct sx sc_cmd_sx; 476 477 struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 478 struct resource *sc_io_res; 479 struct resource *sc_irq_res; 480 struct resource *sc_msix_res; 481 482 void *sc_intr_hdl; 483 bus_size_t sc_io_size; 484 bus_space_tag_t sc_io_tag; 485 bus_space_handle_t sc_io_hdl; 486 /* last pending command address */ 487 uint64_t sc_cmd_addr; 488 /* result of command */ 489 uint32_t sc_cmd_result[2]; 490 /* copy of cmd register */ 491 uint32_t sc_cmd; 492 /* worst case exit latency */ 493 uint32_t sc_exit_lat_max; 494 495 /* offset to operational registers */ 496 uint32_t sc_oper_off; 497 /* offset to capability registers */ 498 uint32_t sc_capa_off; 499 /* offset to runtime registers */ 500 uint32_t sc_runt_off; 501 /* offset to doorbell registers */ 502 uint32_t sc_door_off; 503 504 /* chip specific */ 505 uint16_t sc_erst_max; 506 uint16_t sc_event_idx; 507 uint16_t sc_command_idx; 508 uint16_t sc_imod_default; 509 510 /* number of scratch pages */ 511 uint16_t sc_noscratch; 512 513 uint8_t sc_event_ccs; 514 uint8_t sc_command_ccs; 515 /* number of XHCI device slots */ 516 uint8_t sc_noslot; 517 /* number of ports on root HUB */ 518 uint8_t sc_noport; 519 /* root HUB device configuration */ 520 uint8_t sc_conf; 521 /* step status stage of all control transfers */ 522 uint8_t sc_ctlstep; 523 /* root HUB port event bitmap, max 256 ports */ 524 uint8_t sc_hub_idata[32]; 525 526 /* size of context */ 527 uint8_t sc_ctx_is_64_byte; 528 529 /* vendor string for root HUB */ 530 char sc_vendor[16]; 531 }; 532 533 #define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx) 534 #define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx) 535 #define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED) 536 537 /* prototypes */ 538 539 uint8_t xhci_use_polling(void); 540 usb_error_t xhci_halt_controller(struct xhci_softc *); 541 usb_error_t xhci_reset_controller(struct xhci_softc *); 542 usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); 543 usb_error_t xhci_start_controller(struct xhci_softc *); 544 void xhci_interrupt(unsigned int irq, struct xhci_softc *); 545 void xhci_uninit(struct xhci_softc *); 546 #endif /* _XHCI_H_ */ 547