Searched refs:ZERO_EXTEND_VECTOR_INREG (Results 1 – 16 of 16) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 580 ZERO_EXTEND_VECTOR_INREG, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 68 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
396 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
861 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
1980 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2787 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
3255 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3363 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3381 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4319 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
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| D | LegalizeVectorOps.cpp | 441 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
857 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 325 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
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| D | TargetLowering.cpp | 1678 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1683 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
1752 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; in SimplifyDemandedBits()
2514 case ISD::ZERO_EXTEND_VECTOR_INREG: { in SimplifyDemandedVectorElts()
2532 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) { in SimplifyDemandedVectorElts()
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| D | LegalizeIntegerTypes.cpp | 112 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
4357 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1566 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N); in visit()
9084 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
9136 Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG; in tryToFoldExtendOfConstant()
10601 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) && in visitSIGN_EXTEND_INREG()
18943 Opcode != ISD::ZERO_EXTEND_VECTOR_INREG) in combineTruncationShuffle()
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| D | SelectionDAG.cpp | 3077 case ISD::ZERO_EXTEND_VECTOR_INREG: { in computeKnownBits()
4692 case ISD::ZERO_EXTEND_VECTOR_INREG: in getNode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 85 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
140 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
1437 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(Op), ty(Op), in LowerHvxExtend()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 699 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 374 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
5199 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
5511 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || in combineExtract()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 408 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1103 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1308 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1544 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1801 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v32i16, Custom); in X86TargetLowering()
2017 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG); in X86TargetLowering()
6008 case ISD::ZERO_EXTEND_VECTOR_INREG: in getOpcode_EXTEND_VECTOR_INREG()
6009 return ISD::ZERO_EXTEND_VECTOR_INREG; in getOpcode_EXTEND_VECTOR_INREG()
7469 case ISD::ZERO_EXTEND_VECTOR_INREG: in getFauxShuffleMask()
23402 ShAmt = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(ShAmt), in getTargetVShiftNode()
23416 ShAmt = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(ShAmt), in getTargetVShiftNode()
[all …]
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| D | X86ISelDAGToDAG.cpp | 888 : ISD::ZERO_EXTEND_VECTOR_INREG; in PreprocessISelDAG()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 15814 SubOpcd0 == ISD::ZERO_EXTEND_VECTOR_INREG) && in combineABS()
15816 SubOpcd1 == ISD::ZERO_EXTEND_VECTOR_INREG)) { in combineABS()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 2888 // FastEmit functions for ISD::ZERO_EXTEND_VECTOR_INREG.
6891 …case ISD::ZERO_EXTEND_VECTOR_INREG: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0,…
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