| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 105 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
110 ZeroReg); in runOnMachineFunction()
116 .addReg(ZeroReg) in runOnMachineFunction()
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| D | X86FlagsCopyLowering.cpp | 1054 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass); in rewriteSetCarryExtended() local
1055 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg); in rewriteSetCarryExtended()
1056 ZeroReg = AdjustReg(ZeroReg); in rewriteSetCarryExtended()
1081 .addReg(ZeroReg) in rewriteSetCarryExtended()
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| D | X86FrameLowering.cpp | 589 ZeroReg = InProlog ? X86::RCX in emitStackProbeInline() local
649 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInline()
650 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInline()
651 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInline()
658 .addReg(ZeroReg) in emitStackProbeInline()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Relocation.txt | 56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
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| D | MipsSEInstrInfo.cpp | 87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
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| D | MipsSEISelDAGToDAG.cpp | 85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
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| D | MipsAsmPrinter.cpp | 144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
145 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
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| D | MipsInstrInfo.td | 3124 Register ZeroReg, RegisterOperand GPROpnd> {
3132 (Addiu ZeroReg, tglobaladdr:$in)>;
3134 (Addiu ZeroReg, tblockaddress:$in)>;
3136 (Addiu ZeroReg, tjumptable:$in)>;
3138 (Addiu ZeroReg, tconstpool:$in)>;
3140 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3142 (Addiu ZeroReg, texternalsym:$in)>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2480 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
2495 MIB.addReg(ZeroReg); in copyGPRRegTuple()
3669 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3688 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
3698 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
3699 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
3759 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
3761 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
4414 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4419 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
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| D | AArch64ExpandPseudoInsts.cpp | 73 unsigned ExtendImm, unsigned ZeroReg,
176 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
209 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
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| D | AArch64InstrInfo.h | 145 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
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| D | AArch64ISelDAGToDAG.cpp | 2613 unsigned ZeroReg; in tryShiftAmountMod() local
2617 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
2621 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
2624 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
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| D | AArch64FastISel.cpp | 390 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
393 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4979 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4982 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true, in selectSDiv()
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| D | AArch64ISelLowering.cpp | 11344 unsigned ZeroReg; in replaceZeroVectorStore() local
11347 ZeroReg = AArch64::WZR; in replaceZeroVectorStore()
11350 ZeroReg = AArch64::XZR; in replaceZeroVectorStore()
11354 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT); in replaceZeroVectorStore()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
553 putConstant(I, ZeroReg, 0); in selectCmp()
558 ZeroReg)) in selectCmp()
564 RHSReg, ZeroReg)) in selectCmp()
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| D | ARMFastISel.cpp | 1489 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1492 .addReg(ZeroReg).addImm(1) in SelectCmp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | InstructionSelectorImpl.h | 798 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
802 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
808 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2693 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2713 SrcReg = ZeroReg; in loadImmediate()
2735 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2759 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2788 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
4161 unsigned ZeroReg; in expandDivRem() local
4166 ZeroReg = Mips::ZERO_64; in expandDivRem()
4170 ZeroReg = Mips::ZERO; in expandDivRem()
4194 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4201 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1374 unsigned ZeroReg; in FoldImmediate() local
1377 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1379 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in FoldImmediate()
1384 UseMI.getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
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| D | PPCISelLowering.cpp | 10753 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
10822 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
10867 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
10911 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
11609 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
11642 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
11699 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
11723 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
11736 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 694 Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0); in narrowScalar() local
698 Srcs.push_back(ZeroReg); in narrowScalar()
2033 Register ZeroReg = Zero->getOperand(0).getReg(); in lower() local
2034 MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg}, in lower()
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| D | IRTranslator.cpp | 2148 Register ZeroReg = getOrCreateVReg(*ZeroVal); in translate() local
2149 EntryBuilder->buildCast(Reg, ZeroReg); in translate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 6122 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
6124 ZeroReg, 0); in convertNonUniformLoopRegion()
6125 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()
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