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Searched refs:bankWidth (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/src/r800/
Degbaddrlib.cpp778 if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize) in HwlReduceBankWidthHeight()
783 if (stillGreater && pTileInfo->bankWidth > 1) in HwlReduceBankWidthHeight()
785 while (stillGreater && pTileInfo->bankWidth > 0) in HwlReduceBankWidthHeight()
787 pTileInfo->bankWidth >>= 1; in HwlReduceBankWidthHeight()
789 if (pTileInfo->bankWidth == 0) in HwlReduceBankWidthHeight()
791 pTileInfo->bankWidth = 1; in HwlReduceBankWidthHeight()
796 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
802 (tileSize * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
812 (tileSize * pipes * pTileInfo->bankWidth) in HwlReduceBankWidthHeight()
839 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize; in HwlReduceBankWidthHeight()
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Dciaddrlib.cpp612 pInfo->bankWidth = 1; in HwlSetupTileCfg()
966 tileInfo.banks * tileInfo.bankWidth * in HwlOptimizeTileMode()
1491 tileInfo.bankWidth * tileInfo.bankHeight; in HwlSetupTileInfo()
1502 tileInfo.bankWidth * tileInfo.bankHeight; in HwlSetupTileInfo()
1646 pCfg->info.bankWidth = 1; in ReadGbTileMode()
1750 pCfg->bankWidth = 1 << gbTileMode.f.bank_width; in ReadGbMacroTileCfg()
2199 m_macroTileTable[i].bankWidth * m_macroTileTable[i].bankHeight; in HwlComputeMaxBaseAlignments()
2267 (m_macroTileTable[stencilMacroIndex].bankWidth == in DepthStencilTileCfgMatch()
2268 m_macroTileTable[pOut->macroModeIndex].bankWidth) && in DepthStencilTileCfgMatch()
Dsiaddrlib.cpp226 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth); in ComputeBankEquation()
423 if ((pTileInfo->bankWidth == 1) && in ComputeBankEquation()
2522 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1); in HwlComputeSurfaceCoord2DFromBankPipe()
2536 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth; in HwlComputeSurfaceCoord2DFromBankPipe()
2647 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1)) in HwlPreAdjustBank()
3020 pInfo->bankWidth = 1; in HwlSetupTileCfg()
3082 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width; in ReadGbTileMode()
3528 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight; in HwlComputeMaxBaseAlignments()
3656 key.fields.bankWidth = tileConfig.info.bankWidth; in InitEquationTable()
3718 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth * in InitEquationTable()
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/third_party/mesa3d/src/amd/addrlib/inc/
Daddrinterface.h150 UINT_32 bankWidth : 4; ///< Bank width member
454 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank member
/third_party/mesa3d/src/amd/common/
Dac_surface.c914 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings()
1176 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw; in gfx6_compute_surface()