| /third_party/mesa3d/src/amd/addrlib/src/core/ |
| D | addrlib1.cpp | 430 ValidBaseAlignments(pOut->baseAlign); in ComputeSurfaceInfo()
899 ValidBaseAlignments(pOut->baseAlign); in ComputeFmaskInfo()
1313 pOut->baseAlign = align; in ComputeHtileInfo()
1334 &pOut->baseAlign); in ComputeHtileInfo()
1339 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeHtileInfo()
1402 &pOut->baseAlign, in ComputeCmaskInfo()
1407 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeCmaskInfo()
1848 UINT_32 baseAlign; in ComputeHtileInfo() local
1876 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo); in ComputeHtileInfo()
1884 baseAlign); in ComputeHtileInfo()
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| D | addrlib2.cpp | 323 ValidBaseAlignments(pOut->baseAlign); in ComputeSurfaceInfo()
478 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeHtileInfo()
578 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeCmaskInfo()
713 pOut->baseAlign = localOut.baseAlign; in ComputeFmaskInfo()
722 ValidBaseAlignments(pOut->baseAlign); in ComputeFmaskInfo()
1970 ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0); in ComputeQbStereoInfo()
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| D | addrlib.cpp | 419 pOut->baseAlign = m_maxBaseAlign; in GetMaxAlignments()
459 pOut->baseAlign = m_maxMetaBaseAlign; in GetMaxMetaAlignments()
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| D | addrlib1.h | 246 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
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| /third_party/mesa3d/src/amd/addrlib/src/r800/ |
| D | siaddrlib.h | 154 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
194 UINT_32 baseAlign, UINT_32 pitchAlign,
225 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
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| D | egbaddrlib.cpp | 239 &pOut->baseAlign, in ComputeSurfaceInfoLinear()
282 pOut->baseAlign, in ComputeSurfaceInfoLinear()
401 &pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
430 pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
954 pOut->baseAlign = in ComputeSurfaceAlignmentsMacroTiled()
1217 *pSizeAlign = out.baseAlign; in HwlGetAlignmentInfoMacroTiled()
3199 UINT_32 baseAlign ///< [in] base alignments in ComputeHtileBytes()
3278 pOut->baseAlign = surfOut.baseAlign; in DispatchComputeFmaskInfo()
4019 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); in HwlComputeHtileBaseAlign() local
4026 baseAlign *= pTileInfo->banks; in HwlComputeHtileBaseAlign()
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| D | egbaddrlib.h | 172 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
180 UINT_32 baseAlign, UINT_32 pitchAlign,
292 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
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| D | siaddrlib.cpp | 1272 UINT_32 baseAlign ///< [in] base alignments in HwlComputeHtileBytes()
1275 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign); in HwlComputeHtileBytes()
1685 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentLinear() argument
1840 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentMicroTiled() argument
1860 while ((physicalSliceSize % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
1883 while ((logicalSiceSizeStencil % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
3527 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks * in HwlComputeMaxBaseAlignments() local
3530 if (baseAlign > maxBaseAlign) in HwlComputeMaxBaseAlignments()
3532 maxBaseAlign = baseAlign; in HwlComputeMaxBaseAlignments()
3594 pOut->baseAlign *= numMacroTiles; in HwlComputeSurfaceAlignmentsMacroTiled()
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| D | ciaddrlib.cpp | 2198 UINT_32 baseAlign = tileSize * pipes * m_macroTileTable[i].banks * in HwlComputeMaxBaseAlignments() local
2201 if (baseAlign > maxBaseAlign) in HwlComputeMaxBaseAlignments()
2203 maxBaseAlign = baseAlign; in HwlComputeMaxBaseAlignments()
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| /third_party/mesa3d/src/amd/addrlib/inc/ |
| D | addrinterface.h | 599 UINT_32 baseAlign; ///< Base address alignment member
909 UINT_32 baseAlign; ///< Base alignment member
1128 UINT_32 baseAlign; ///< Base alignment member
1325 UINT_32 baseAlign; ///< Base address alignment member
2326 UINT_32 baseAlign; ///< Maximum base alignment in bytes member
2500 UINT_32 baseAlign; ///< Base address alignment member
2779 UINT_32 baseAlign; ///< Base alignment member
2987 UINT_32 baseAlign; ///< Base alignment member
3213 UINT_32 baseAlign; ///< Base alignment member
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| /third_party/mesa3d/src/amd/addrlib/src/gfx9/ |
| D | gfx9addrlib.h | 517 UINT_32 baseAlign; in ComputeSurfaceBaseAlignTiled() local
521 baseAlign = GetBlockSize(swizzleMode); in ComputeSurfaceBaseAlignTiled()
525 baseAlign = 256; in ComputeSurfaceBaseAlignTiled()
528 return baseAlign; in ComputeSurfaceBaseAlignTiled()
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| D | gfx9addrlib.cpp | 256 pOut->baseAlign = align; in HwlComputeHtileInfo()
345 pOut->baseAlign = Max(numCompressBlkPerMetaBlk >> 1, sizeAlign); in HwlComputeCmaskInfo()
4288 pOut->baseAlign = ComputeSurfaceBaseAlignTiled(pIn->swizzleMode); in HwlComputeSurfaceInfoTiled()
4300 pOut->baseAlign = Max(pOut->baseAlign, m_pipeInterleaveBytes * m_pipes * m_se); in HwlComputeSurfaceInfoTiled()
4305 pOut->baseAlign = Max(pOut->baseAlign, PrtAlignment); in HwlComputeSurfaceInfoTiled()
4390 … pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? (pIn->bpp / 8) : alignment; in HwlComputeSurfaceInfoLinear()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.c | 553 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign; in ac_addrlib_create()
695 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256; in gfx6_compute_level()
834 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign); in gfx6_compute_level()
908 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign); in gfx6_surface_settings()
1327 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign); in gfx6_compute_surface()
1744 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign)); in gfx9_compute_miptree()
1745 surf->u.gfx9.zs.stencil_offset = align(surf->surf_size, out.baseAlign); in gfx9_compute_miptree()
1765 surf->surf_alignment_log2 = util_logbase2(out.baseAlign); in gfx9_compute_miptree()
1830 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign); in gfx9_compute_miptree()
2049 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign); in gfx9_compute_miptree()
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| /third_party/mesa3d/src/amd/addrlib/src/gfx10/ |
| D | gfx10addrlib.cpp | 186 pOut->baseAlign = Max(metaBlkSize, 1u << (m_pipesLog2 + 11u)); in HwlComputeHtileInfo()
305 pOut->baseAlign = metaBlkSize; in HwlComputeCmaskInfo()
3578 pOut->baseAlign = blockSize; in ComputeSurfaceInfoMicroTiled()
3680 pOut->baseAlign = blockSize; in ComputeSurfaceInfoMacroTiled()
4822 … pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? elementBytes : 256; in HwlComputeSurfaceInfoLinear()
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| /third_party/mesa3d/src/amd/addrlib/src/gfx11/ |
| D | gfx11addrlib.cpp | 187 pOut->baseAlign = Max(metaBlkSize, 1u << (m_pipesLog2 + 11u)); in HwlComputeHtileInfo()
3061 pOut->baseAlign = blockSize; in ComputeSurfaceInfoMicroTiled()
3163 pOut->baseAlign = blockSize; in ComputeSurfaceInfoMacroTiled()
4230 … pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? elementBytes : 256; in HwlComputeSurfaceInfoLinear()
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