Searched refs:block_sel (Results 1 – 4 of 4) sorted by relevance
35 struct ac_spm_block_select *block_sel, *new_block_sel; in ac_spm_get_block_select() local39 if (spm_trace->block_sel[i].b->b->b->gpu_block == block->b->b->gpu_block) in ac_spm_get_block_select()40 return &spm_trace->block_sel[i]; in ac_spm_get_block_select()45 block_sel = realloc(spm_trace->block_sel, num_block_sel * sizeof(*block_sel)); in ac_spm_get_block_select()46 if (!block_sel) in ac_spm_get_block_select()50 spm_trace->block_sel = block_sel; in ac_spm_get_block_select()53 new_block_sel = &spm_trace->block_sel[spm_trace->num_block_sel - 1]; in ac_spm_get_block_select()85 struct ac_spm_block_select *block_sel, in ac_spm_map_counter() argument89 if (block_sel->b->b->b->gpu_block == SQ) { in ac_spm_map_counter()113 for (unsigned i = 0; i < block_sel->num_counters; i++) { in ac_spm_map_counter()[all …]
106 struct ac_spm_block_select *block_sel; member
78 struct ac_spm_block_select *block_sel = &spm_trace->block_sel[b]; in radv_emit_spm_counters() local79 struct ac_pc_block_base *regs = block_sel->b->b->b; in radv_emit_spm_counters()81 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, block_sel->grbm_gfx_index); in radv_emit_spm_counters()83 for (unsigned c = 0; c < block_sel->num_counters; c++) { in radv_emit_spm_counters()84 const struct ac_spm_counter_select *cntr_sel = &block_sel->counters[c]; in radv_emit_spm_counters()
764 struct ac_spm_block_select *block_sel = &spm_trace->block_sel[b]; in si_emit_spm_counters() local765 struct ac_pc_block_base *regs = block_sel->b->b->b; in si_emit_spm_counters()767 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, block_sel->grbm_gfx_index); in si_emit_spm_counters()769 for (unsigned c = 0; c < block_sel->num_counters; c++) { in si_emit_spm_counters()770 const struct ac_spm_counter_select *cntr_sel = &block_sel->counters[c]; in si_emit_spm_counters()