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Searched refs:buildInstr (Results 1 – 20 of 20) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h333 MachineInstrBuilder buildInstr(unsigned Opcode);
524 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
530 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src}); in buildPtrToInt()
535 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src}); in buildIntToPtr()
540 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); in buildBitcast()
545 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src}); in buildAddrSpaceCast()
1229 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1246 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1262 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1268 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
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DConstantFoldingMIRBuilder.h28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
69 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);
DLegalizationArtifactCombiner.h74 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
159 Builder.buildInstr( in tryCombineSExt()
214 Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {}); in tryFoldImplicitDef()
343 Builder.buildInstr(ConvertOp, {DstRegs[j]}, {TmpRegs[j]}); in tryCombineMerges()
386 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); in tryCombineMerges()
DCSEMIRBuilder.h94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { in buildInstr() function in MachineIRBuilder
123 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
138 auto MIB = buildInstr(TargetOpcode::DBG_VALUE); in buildConstDbgValue()
158 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
167 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); in buildDynStackAlloc()
177 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); in buildFrameIndex()
190 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); in buildGlobalValue()
198 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {}) in buildJumpTable()
221 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}); in buildPtrAdd()
246 auto MIB = buildInstr(TargetOpcode::G_PTR_MASK); in buildPtrMask()
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DLegalizerHelper.cpp768 MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut}, in narrowScalar()
776 MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut}, in narrowScalar()
824 MIRBuilder.buildInstr(ExtLoad) in narrowScalar()
929 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); in narrowScalar()
1007 MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt}); in narrowScalar()
1055 .buildInstr(TargetOpcode::G_ASHR, {NarrowTy}, in narrowScalar()
1063 .buildInstr( in narrowScalar()
1089 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, in narrowScalar()
1106 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()}); in widenScalarSrc()
1113 auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy}, in narrowScalarSrc()
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DCSEMIRBuilder.cpp137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
179 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
183 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
200 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
DIRTranslator.cpp303 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
319 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags); in translateFSub()
333 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags); in translateFNeg()
356 MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1}, in translateCompare()
634 Cond = MIB.buildInstr(TargetOpcode::G_XOR, {i1Ty}, {Cond, True}, None) in emitSwitchCase()
1019 MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]}, in translateSelect()
1050 MIRBuilder.buildInstr(Opcode, {Res}, {Op}); in translateCast()
1174 auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD); in getStackGuard()
1194 MIRBuilder.buildInstr(Op) in translateOverflowIntrinsic()
1280 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
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DCombinerHelper.cpp761 auto MIB = MIRBuilder.buildInstr(NewOpcode); in applyCombineIndexedLoadStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp627 auto SubRegCopy = MIB.buildInstr(TargetOpcode::COPY, {To}, {}) in selectSubregisterCopy()
1006 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB); in selectCompareBranch()
1125 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg}); in selectVectorSHL()
1171 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg}); in selectVectorASHR()
1173 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg}); in selectVectorASHR()
1218 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {}); in materializeLargeCMVal()
1230 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
1279 auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {}) in preISelLower()
1317 MIB.buildInstr(Is64Bit ? AArch64::UBFMXri : AArch64::UBFMWri, in earlySelectSHL()
1726 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {}) in select()
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DAArch64CallLowering.cpp329 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
348 MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0); in lowerReturn()
806 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerTailCall()
902 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0); in lowerTailCall()
964 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerCall()
1024 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) in lowerCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp291 MachineInstrBuilder Bitcast = MIRBuilder.buildInstr( in legalizeCustom()
321 if (!MIRBuilder.buildInstr(Opcode) in SelectMSA3OpIntrinsic()
336 MIRBuilder.buildInstr(Opcode) in MSA3OpIntrinsicToGeneric()
348 MIRBuilder.buildInstr(Opcode) in MSA2OpIntrinsicToGeneric()
375 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); in legalizeIntrinsic()
DMipsInstructionSelector.cpp144 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
150 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
157 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
163 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
165 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
505 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
518 MachineInstrBuilder PairF64 = B.buildInstr( in select()
707 MachineInstrBuilder MIB = B.buildInstr( in select()
DMipsCallLowering.cpp147 .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64 in assignValueToReg()
157 MIRBuilder.buildInstr(Mips::MTC1) in assignValueToReg()
259 .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 in assignValueToReg()
267 .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 in assignValueToReg()
275 MIRBuilder.buildInstr(Mips::MFC1) in assignValueToReg()
564 MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN); in lowerCall()
667 MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0); in lowerCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp691 B.buildInstr(AMDGPU::G_UNMERGE_VALUES) in split64BitValueForMapping()
776 B.buildInstr(TargetOpcode::IMPLICIT_DEF) in executeInWaterfallLoop()
805 B.buildInstr(TargetOpcode::PHI) in executeInWaterfallLoop()
813 B.buildInstr(TargetOpcode::G_PHI) in executeInWaterfallLoop()
865 B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64) in executeInWaterfallLoop()
875 B.buildInstr(WaveAndOpc) in executeInWaterfallLoop()
959 B.buildInstr(CmpOp) in executeInWaterfallLoop()
968 B.buildInstr(WaveAndOpc) in executeInWaterfallLoop()
995 B.buildInstr(AndSaveExecOpc) in executeInWaterfallLoop()
1002 B.buildInstr(XorTermOpc) in executeInWaterfallLoop()
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DAMDGPULegalizerInfo.cpp1207 B.buildInstr(AMDGPU::S_GETREG_B32) in getSegmentAperture()
1213 B.buildInstr(TargetOpcode::G_SHL) in getSegmentAperture()
1343 B.buildInstr(TargetOpcode::G_PTRTOINT) in legalizeAddrSpaceCast()
1398 auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src}); in legalizeFceil()
1658 MachineInstrBuilder MIB = B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET) in buildPCRelGlobalAddress()
1796 B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG) in legalizeAtomicCmpXChg()
2047 B.buildInstr(AMDGPU::S_DENORM_MODE) in toggleSPDenormMode()
2056 B.buildInstr(AMDGPU::S_SETREG_IMM32_B32) in toggleSPDenormMode()
2370 B.buildInstr(AMDGPU::SI_IF) in legalizeIntrinsic()
2375 B.buildInstr(AMDGPU::SI_ELSE) in legalizeIntrinsic()
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DAMDGPUInstructionSelector.cpp948 B.buildInstr(AMDGPU::V_MOV_B32_e32) in splitBufferOffsets()
953 B.buildInstr(AMDGPU::V_MOV_B32_e32) in splitBufferOffsets()
1004 MachineInstrBuilder MIB = B.buildInstr(Opc) in selectStoreIntrinsic()
DAMDGPUCallLowering.cpp307 B.buildInstr(AMDGPU::S_ENDPGM) in lowerReturn()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp394 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
438 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
486 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp517 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN); in lowerCall()
581 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP) in lowerCall()