Searched refs:buildMerge (Results 1 – 13 of 13) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 204 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
624 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
679 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)}); in narrowScalar()
699 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs); in narrowScalar()
750 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
782 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); in narrowScalar()
934 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); in narrowScalar()
1074 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
1094 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); in narrowScalar()
1280 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); in widenScalarMergeValues()
[all …]
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| D | CallLowering.cpp | 323 MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs); in handleAssignments()
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| D | MachineIRBuilder.cpp | 552 buildMerge(Res, Ops); in buildSequence()
572 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
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| D | CombinerHelper.cpp | 286 Builder.buildMerge(NewDstReg, Ops); in applyCombineShuffleVector()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
478 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs); in lowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 495 B.buildMerge(OrigRegs[0], Regs); in packSplitRegsToOrigType()
549 auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt)); in packSplitRegsToOrigType()
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| D | AMDGPULegalizerInfo.cpp | 1295 B.buildMerge(Dst, {Src, HighAddr.getReg(0)}); in legalizeAddrSpaceCast()
1349 B.buildMerge(BuildPtr, {SrcAsInt, ApertureReg}); in legalizeAddrSpaceCast()
1459 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)}); in legalizeIntrinsicTrunc()
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| D | AMDGPURegisterBankInfo.cpp | 927 B.buildMerge(LLT::scalar(64), in executeInWaterfallLoop()
982 auto Merge = B.buildMerge(OpTy, ReadlanePieces); in executeInWaterfallLoop()
1279 return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0); in handleD16VData()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 370 Builder.buildMerge(DefReg, Regs); in tryCombineMerges()
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| D | MachineIRBuilder.h | 785 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 392 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); in assignCustomValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 220 MIRBuilder.buildMerge(ArgsReg, VRegs); in handleSplit()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 325 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)}) in lowerReturn()
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