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Searched refs:buildUndef (Results 1 – 10 of 10) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp152 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()
185 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()
266 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
DLegalizerHelper.cpp219 MIRBuilder.buildUndef(CurResultReg); in insertParts()
618 MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg()); in narrowScalar()
1160 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); in moreElementsVectorSrc()
1170 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); in moreElementsVectorSrc()
1270 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()
2340 MIRBuilder.buildUndef(TmpReg); in fewerElementsVectorImplicitDef()
2375 MIRBuilder.buildUndef(AccumDstReg); in fewerElementsVectorBasic()
2856 UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0); in fewerElementsVectorBuildVector()
4215 Val = MIRBuilder.buildUndef(DstTy).getReg(0); in lowerShuffleVector()
4230 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); in lowerShuffleVector()
DCallLowering.cpp145 MIRBuilder.buildUndef(Dst); in packRegs()
DMachineIRBuilder.cpp557 buildUndef(ResIn); in buildSequence()
568 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder
DIRTranslator.cpp1519 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()
1773 MIRBuilder.buildUndef(Undef); in translateLandingPad()
2141 EntryBuilder->buildUndef(Reg); in translate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp249 auto ImpDef = B.buildUndef(BigTy); in unpackRegsToOrigType()
639 B.buildUndef(VRegs[Idx][I]); in lowerFormalArguments()
DAMDGPULegalizerInfo.cpp1553 B.buildUndef(Dst); in legalizeExtractVectorElt()
1583 B.buildUndef(Dst); in legalizeInsertVectorElt()
DAMDGPURegisterBankInfo.cpp763 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp323 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
336 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h756 MachineInstrBuilder buildUndef(const DstOp &Res);