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/third_party/mesa3d/src/intel/tools/tests/gen6/
Dsendc.expected1 32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 01 88
2 32 00 80 05 c8 0f 00 20 20 00 8d 00 00 90 01 90
3 32 00 80 05 c8 0f 00 20 40 00 8d 00 00 91 01 82
4 32 00 60 05 c8 0f 00 20 20 00 8d 00 01 94 09 8c
5 32 00 80 05 c8 0f 00 20 20 00 8d 00 01 90 09 94
6 32 00 60 05 c8 0f 00 20 20 00 8d 00 01 84 09 0e
7 32 00 60 05 c8 0f 00 20 20 00 8d 00 02 94 09 8e
8 32 00 80 05 c8 0f 00 20 20 00 8d 00 01 80 09 18
9 32 00 80 05 c8 0f 00 20 20 00 8d 00 02 90 09 98
10 32 00 60 05 c8 0f 00 20 20 00 8d 00 00 84 09 0c
[all …]
Dmad.expected4 5b 01 60 00 01 00 1e 03 c8 41 c1 3f 0a 20 87 05
5 5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 47 05
6 5b 11 60 06 00 00 1e 04 c8 21 20 80 0c 20 07 06
7 5b 11 60 00 01 00 1e 02 c8 a1 01 39 14 20 87 04
10 5b 01 60 80 01 00 1e 04 c8 a1 21 c0 09 20 87 02
11 5b 05 60 80 01 00 0e 04 48 d1 06 29 c8 50 c5 1a
12 5b 01 60 00 00 02 1e 2a c8 91 22 80 08 04 00 10
13 5b 01 60 00 20 02 1e 3a c8 91 03 39 6a 20 47 0d
14 5b 01 60 00 a0 02 1e 4c c8 81 23 40 80 20 47 0d
15 5b 01 60 80 00 00 1e 2c c8 b1 02 39 52 20 87 06
[all …]
Dlrp.expected2 5c 01 60 00 01 00 1e 01 c8 21 02 39 08 20 07 10
3 5c 11 60 00 01 00 1e 02 c8 21 00 39 0c 20 47 03
4 5c 01 60 80 00 00 1e 07 c8 c1 00 39 1e 20 87 04
5 5c 11 60 80 00 00 1e 12 c8 a1 01 39 1a 20 87 09
6 5c 11 60 00 00 00 1e 02 c8 21 01 39 04 20 07 02
7 5c 01 60 80 01 00 1e 01 c8 61 00 39 1a 20 07 01
8 5c 11 60 80 01 00 1e 02 c8 91 00 39 36 20 47 04
/third_party/mesa3d/src/intel/tools/tests/gen8/
Dmad.expected1 5b 01 60 00 00 00 1e 1a c8 61 21 00 05 20 47 01
2 5b 01 80 00 00 00 1e 15 c8 31 01 39 16 20 c7 02
3 5b 01 60 00 00 d8 1e 40 c8 e1 03 39 50 20 07 17
4 5b 01 60 00 40 d8 1e 4a c8 21 03 39 30 20 87 12
5 5b 11 60 00 00 d8 1e 1b c8 01 03 39 d4 20 47 06
6 5b 01 60 00 00 dc 1e 1d c8 71 01 39 36 20 47 06
8 5b 01 60 00 40 00 1e 7c 01 f0 00 39 1c 04 c8 03
9 5b 01 60 00 00 04 1e 7c 01 f0 00 39 1c 04 c8 03
10 5b 01 60 06 00 00 1e 09 c8 31 20 80 08 20 c7 03
11 5b 01 80 06 00 00 1e 0f c8 41 20 80 0c 20 07 06
[all …]
Dcsel.expected1 12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02
2 12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02
4 12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a
6 12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01
7 12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01
8 12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12
9 12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12
10 12 01 80 05 40 00 1e 45 c8 b1 00 39 16 20 c7 10
Dmov.expected31 01 00 60 00 c8 32 40 29 a0 00 00 00 00 00 00 00
35 01 00 60 00 c8 3a 80 2b e0 0b 69 00 00 00 00 00
36 01 10 60 00 c8 3a 40 2d 40 00 00 00 00 00 00 00
65 01 00 60 00 c8 0a 00 21 40 00 00 00 00 00 00 00
73 01 10 60 00 c8 32 00 24 40 00 00 00 00 00 00 00
85 01 00 60 00 c8 56 e0 20 00 00 00 00 00 00 00 00
91 01 00 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
92 01 10 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
112 01 10 60 00 c8 0a 60 20 40 40 00 00 00 00 00 00
115 01 10 60 00 c8 56 80 20 00 00 00 00 00 00 00 00
Dsel.expected17 02 00 60 05 c8 32 40 22 a0 00 00 32 a8 00 00 00
24 02 00 61 00 c8 32 20 21 40 00 00 32 40 40 00 00
25 02 10 61 00 c8 32 80 21 40 00 00 32 40 40 00 00
26 02 00 60 04 c8 32 a0 20 40 00 00 32 50 00 00 00
27 02 10 60 04 c8 32 60 24 40 00 00 32 50 00 00 00
28 02 10 60 05 c8 32 60 21 60 04 69 32 60 00 00 00
Dcmp.expected2 10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00
10 10 00 60 01 c8 32 00 24 d0 20 00 32 80 08 69 00
13 10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00
14 10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00
15 10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00
18 10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00
44 10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00
45 10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00
Dbfe.expected1 18 01 60 00 00 90 1e 22 c8 91 05 39 3c 20 c7 16
2 18 01 80 00 00 90 1e 0d c8 c1 02 39 e6 20 87 1f
3 18 01 60 00 00 48 1e 12 c8 11 01 39 20 20 47 0c
4 18 01 80 00 00 48 1e 0d c8 b1 00 39 54 20 47 01
/third_party/mesa3d/src/intel/tools/tests/gen9/
Dmad.expected1 5b 01 60 00 00 00 1e 1a c8 61 21 00 05 20 47 01
2 5b 01 80 00 00 00 1e 0e c8 c1 00 39 08 20 07 01
3 5b 01 60 00 00 d8 1e 40 c8 e1 03 39 50 20 07 17
4 5b 01 60 00 40 d8 1e 50 c8 21 03 39 30 20 07 14
5 5b 11 60 00 00 d8 1e 1b c8 01 03 39 d4 20 47 06
8 5b 01 60 00 00 dc 1e 1d c8 71 01 39 36 20 47 06
9 5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 07 10
10 5b 01 80 06 00 00 1e 07 c8 41 20 80 0c 20 07 04
11 5b 01 60 00 00 04 1e 20 c8 f1 21 c0 04 20 c7 03
12 5b 01 80 00 00 04 1e 38 c8 61 23 c0 04 20 47 01
[all …]
Dcsel.expected1 12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02
2 12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02
4 12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a
6 12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01
7 12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01
8 12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12
9 12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12
10 12 01 80 05 40 00 1e 45 c8 11 04 39 82 20 c7 10
Dmov.expected27 01 00 60 00 c8 32 00 2a a0 00 00 00 00 00 00 00
31 01 00 60 00 c8 3a 80 2b e0 0b 69 00 00 00 00 00
32 01 10 60 00 c8 3a 40 2d 40 00 00 00 00 00 00 00
61 01 00 60 00 c8 0a 00 21 40 00 00 00 00 00 00 00
68 01 10 60 00 c8 32 00 24 40 00 00 00 00 00 00 00
76 01 00 60 00 c8 56 e0 20 00 00 00 00 00 00 00 00
81 01 00 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
82 01 10 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
102 01 10 60 00 c8 0a 60 20 40 40 00 00 00 00 00 00
105 01 10 60 00 c8 56 80 20 00 00 00 00 00 00 00 00
Dsel.expected17 02 00 60 05 c8 32 40 22 a0 00 00 32 a8 00 00 00
24 02 00 61 00 c8 32 20 21 40 00 00 32 40 40 00 00
25 02 10 61 00 c8 32 80 21 40 00 00 32 40 40 00 00
26 02 00 60 04 c8 32 a0 20 40 00 00 32 50 00 00 00
27 02 10 60 04 c8 32 60 24 40 00 00 32 50 00 00 00
28 02 10 60 05 c8 32 60 21 60 04 69 32 60 00 00 00
Dcmp.expected2 10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00
10 10 00 60 01 c8 32 c0 2a d0 20 00 32 80 08 69 00
13 10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00
14 10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00
15 10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00
18 10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00
40 10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00
41 10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00
/third_party/mesa3d/src/intel/tools/tests/gen7/
Dmad.expected6 5b 01 60 06 00 00 1e 09 c8 31 20 80 08 20 c7 03
7 5b 11 60 06 00 00 1e 04 c8 21 20 80 0c 20 07 05
11 5b 01 60 00 20 02 1e 35 c8 41 03 39 2a 20 47 05
12 5b 01 60 00 a0 02 1e 47 c8 81 20 00 05 20 47 05
13 5b 01 60 80 00 00 1e 28 c8 71 02 39 4a 20 87 02
14 5b 11 60 00 00 02 1e 43 c8 11 24 80 0c 04 90 00
15 5b 11 60 00 20 02 1e 25 c8 31 02 39 ae 20 c7 15
16 5b 11 60 00 a0 02 1e 06 c8 d1 25 40 05 20 c7 15
17 5b 11 60 80 00 00 1e 09 c8 71 00 39 ec 20 47 1a
21 5b 01 60 00 80 00 1e 7d c8 b1 20 00 1a 20 87 01
[all …]
/third_party/ffmpeg/tests/ref/fate/
Dsub-scc-remux3 00:00:01:04 9420 9420 94da 94da c2d5 52ce 20c8 4552 20a1 947a 947a 20c2 d552 ce20 c845 5220 a180 94…
15c8 4552 20a1 94d0 94d0 ad20 5b20 43f2 eff7 6420 43ef 6ef4 e96e 75e5 7320 d368 ef75 f4e9 6e67 205d …
19 00:00:25:26 9420 9420 1370 1370 57c8 4f20 c152 4520 d94f d52c 94d0 94d0 57c8 4f20 c152 4520 d34f 20…
21 00:00:29:22 9420 9420 94d6 94d6 4920 c1cd 20c1 5254 c8d5 522c 9476 9476 cb49 cec7 204f 4620 54c8 45…
25 …52 20cb ce49 c7c8 542c 9454 9454 5749 4c4c 20d9 4fd5 2043 4fcd 4520 5749 54c8 20cd 4580 94f4 94f4 …
29 00:00:40:12 9420 9420 94d0 94d0 cdd9 204c 4945 c745 2c80 9470 9470 4920 574f d54c c420 c245 20c8 4f…
31 00:00:42:16 9420 9420 13d6 13d6 57c8 c154 2049 d320 d94f d552 20ce c1cd 4520 bf80 9470 9470 c245 c4…
37 00:00:51:26 9420 9420 94ce 94ce 5b20 ce61 f2f2 61f4 eff2 205d 946e 946e 54c8 4520 5749 d345 20d3 49…
39 00:00:53:23 9420 9420 94ce 94ce 57c1 d320 54c8 4520 4649 52d3 5420 544f 204a 4f49 ce80 946e 946e cb…
43 00:01:00:08 9420 9420 946e 946e d349 5220 4cc1 d5ce 4345 4c4f 5420 54c8 4520 c252 c1d6 453b 942c 94…
[all …]
/third_party/mesa3d/src/intel/tools/tests/gen7.5/
Dmad.expected6 5b 01 60 06 00 00 1e 09 c8 31 20 80 08 20 c7 03
7 5b 01 80 06 00 00 1e 0f c8 41 20 80 0c 20 07 06
8 5b 01 60 00 00 02 1e 20 c8 f1 21 c0 04 20 c7 03
9 5b 01 80 00 00 02 1e 38 c8 61 23 c0 04 20 47 01
17 5b 01 60 00 20 02 1e 35 c8 41 03 39 2a 20 47 05
18 5b 01 60 00 a0 02 1e 47 c8 81 20 00 05 20 47 05
19 5b 01 80 00 20 02 1e 60 c8 e1 05 39 ac 20 87 15
20 5b 01 80 00 a0 02 1e 05 c8 c1 25 00 05 20 87 15
25 5b 01 60 00 60 00 1e 02 c8 61 00 39 0a 04 80 03
26 5b 01 80 00 60 00 1e 02 c8 81 00 39 0c 04 40 06
[all …]
/third_party/typescript/tests/baselines/reference/
DcommentsClass.js53 class c8 { class
63 var i8 = new c8();
64 var i8_c = c8;
129 var c8 = /** @class */ (function () { function
132 function c8() { function
136 return c8;
138 var i8 = new c8();
139 var i8_c = c8;
188 declare class c8 {
195 declare var i8: c8;
[all …]
DcommentsClass.types109 class c8 {
110 >c8 : c8
123 var i8 = new c8();
124 >i8 : c8
125 >new c8() : c8
126 >c8 : typeof c8
128 var i8_c = c8;
129 >i8_c : typeof c8
130 >c8 : typeof c8
DconstDeclarations-errors.types20 for(const c8 = 0; c8 < 1; c8++) { }
21 >c8 : 0
23 >c8 < 1 : boolean
24 >c8 : 0
26 >c8++ : number
27 >c8 : any
DconstDeclarations-errors.symbols19 for(const c8 = 0; c8 < 1; c8++) { }
20 >c8 : Symbol(c8, Decl(constDeclarations-errors.ts, 8, 9))
21 >c8 : Symbol(c8, Decl(constDeclarations-errors.ts, 8, 9))
22 >c8 : Symbol(c8, Decl(constDeclarations-errors.ts, 8, 9))
DconstDeclarations-errors.js10 for(const c8 = 0; c8 < 1; c8++) { }
25 for (const c8 = 0; c8 < 1; c8++) { }
DcommentsClass.symbols103 class c8 {
104 >c8 : Symbol(c8, Decl(commentsClass.ts, 47, 14))
108 >s1 : Symbol(c8.s1, Decl(commentsClass.ts, 51, 10))
117 var i8 = new c8();
119 >c8 : Symbol(c8, Decl(commentsClass.ts, 47, 14))
121 var i8_c = c8;
123 >c8 : Symbol(c8, Decl(commentsClass.ts, 47, 14))
/third_party/node/deps/npm/node_modules/@isaacs/cliui/build/
Dindex.cjs15 /* c8 ignore start */
17 /* c8 ignore stop */
111 /* c8 ignore start */
113 /* c8 ignore stop */
146 /* c8 ignore start */
148 /* c8 ignore stop */
206 /* c8 ignore start */
208 /* c8 ignore stop */
235 /* c8 ignore start */
237 /* c8 ignore stop */
[all …]
/third_party/elfutils/tests/
Drun-strip-remove-keep.sh44 [ 5] .dynstr STRTAB 080481c8 0001c8 00008e 0 A 0 0 1
60 [21] .bss NOBITS 080495c8 0005c8 00001c 0 WA 0 0 4
61 [22] .comment PROGBITS 00000000 0005c8 000170 0 0 0 1
79 [ 5] .dynstr NOBITS 080481c8 000114 00008e 0 A 0 0 1
95 [21] .sbss PROGBITS 080495c8 000120 000000 0 W 0 0 1
96 [22] .bss NOBITS 080495c8 000120 00001c 0 WA 0 0 4
130 [ 5] .dynstr STRTAB 080481c8 0001c8 00008e 0 A 0 0 1
146 [21] .bss NOBITS 080495c8 0005c8 00001c 0 WA 0 0 4
147 [22] .comment PROGBITS 00000000 0005c8 000170 0 0 0 1
166 [ 5] .dynstr NOBITS 080481c8 000114 00008e 0 A 0 0 1
[all …]

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