Searched refs:cmp_instr (Results 1 – 3 of 3) sorted by relevance
| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_nir.cpp | 782 nir_alu_instr *cmp_instr = in optimize_predicate() local
785 switch (cmp_instr->op) { in optimize_predicate()
807 brw_swizzle_for_size(nir_op_infos[cmp_instr->op].input_sizes[0]); in optimize_predicate()
810 assert(nir_op_infos[cmp_instr->op].num_inputs == 2); in optimize_predicate()
812 nir_alu_type type = nir_op_infos[cmp_instr->op].input_types[i]; in optimize_predicate()
813 unsigned bit_size = nir_src_bit_size(cmp_instr->src[i].src); in optimize_predicate()
815 op[i] = get_nir_src(cmp_instr->src[i].src, type, 4); in optimize_predicate()
817 brw_swizzle_for_nir_swizzle(cmp_instr->src[i].swizzle); in optimize_predicate()
822 brw_cmod_for_nir_comparison(cmp_instr->op))); in optimize_predicate()
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| /third_party/node/deps/v8/src/compiler/backend/s390/ |
| D | code-generator-s390.cc | 527 #define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr) \ argument
536 __ cmp_instr(i.InputRegister(0), operand); \
542 __ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
548 __ cmp_instr(i.InputRegister(0), i.InputImmediate(1)); \
555 __ cmp_instr(i.InputRegister(0), i.InputStackSlot(1)); \
560 #define ASSEMBLE_COMPARE32(cmp_instr, cmpl_instr) \ argument
569 __ cmp_instr(i.InputRegister(0), operand); \
575 __ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
581 __ cmp_instr(i.InputRegister(0), i.InputImmediate(1)); \
588 __ cmp_instr(i.InputRegister(0), i.InputStackSlot32(1)); \
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| /third_party/node/deps/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 384 #define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr) \ argument
391 __ cmp_instr(i.InputRegister(0), i.InputRegister(1), cr); \
397 __ cmp_instr##i(i.InputRegister(0), i.InputImmediate(1), cr); \
403 #define ASSEMBLE_FLOAT_COMPARE(cmp_instr) \ argument
406 __ cmp_instr(i.InputDoubleRegister(0), i.InputDoubleRegister(1), cr); \
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