Searched refs:cntr_sel (Results 1 – 3 of 3) sorted by relevance
92 struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0]; in ac_spm_map_counter() local97 cntr_sel->sel0 |= S_036700_PERF_SEL(counter->event_id) | in ac_spm_map_counter()100 cntr_sel->active |= 0x3; in ac_spm_map_counter()114 struct ac_spm_counter_select *cntr_sel = &block_sel->counters[i]; in ac_spm_map_counter() local115 int index = ffs(~cntr_sel->active) - 1; in ac_spm_map_counter()119 cntr_sel->sel0 |= S_037004_PERF_SEL(counter->event_id) | in ac_spm_map_counter()124 cntr_sel->sel0 |= S_037004_PERF_SEL1(counter->event_id) | in ac_spm_map_counter()128 cntr_sel->sel1 |= S_037008_PERF_SEL2(counter->event_id) | in ac_spm_map_counter()132 cntr_sel->sel1 |= S_037008_PERF_SEL3(counter->event_id) | in ac_spm_map_counter()140 cntr_sel->active |= 1 << index; in ac_spm_map_counter()
70 const struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0]; in radv_emit_spm_counters() local74 radeon_emit(cs, cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */ in radv_emit_spm_counters()84 const struct ac_spm_counter_select *cntr_sel = &block_sel->counters[c]; in radv_emit_spm_counters() local86 if (!cntr_sel->active) in radv_emit_spm_counters()90 radeon_emit(cs, cntr_sel->sel0); in radv_emit_spm_counters()93 radeon_emit(cs, cntr_sel->sel1); in radv_emit_spm_counters()
756 const struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0]; in si_emit_spm_counters() local760 radeon_emit(cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */ in si_emit_spm_counters()770 const struct ac_spm_counter_select *cntr_sel = &block_sel->counters[c]; in si_emit_spm_counters() local772 if (!cntr_sel->active) in si_emit_spm_counters()776 radeon_emit(cntr_sel->sel0); in si_emit_spm_counters()779 radeon_emit(cntr_sel->sel1); in si_emit_spm_counters()