| /third_party/mesa3d/src/intel/isl/ |
| D | isl_emit_cpb.c | 54 struct GENX(3DSTATE_CPSIZE_CONTROL_BUFFER) cpb = { in isl_genX()
81 cpb.Width = (info->surf->logical_level0_px.width * 8) - 1; in isl_genX()
82 cpb.Height = (info->surf->logical_level0_px.height * 8) - 1; in isl_genX()
83 cpb.Depth = info->view->array_len - 1; in isl_genX()
84 cpb.RenderTargetViewExtent = cpb.Depth; in isl_genX()
86 cpb.SurfLOD = info->view->base_level; in isl_genX()
87 cpb.MinimumArrayElement = info->view->base_array_layer; in isl_genX()
88 cpb.SurfaceType = SURFTYPE_2D; in isl_genX()
89 cpb.SurfacePitch = info->surf->row_pitch_B - 1; in isl_genX()
90 cpb.MOCS = info->mocs; in isl_genX()
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| D | isl.h | 1279 } cpb; member
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| D | isl.c | 313 dev->cpb.size = _3DSTATE_CPSIZE_CONTROL_BUFFER_length(info) * 4; in isl_device_init()
314 dev->cpb.offset = in isl_device_init()
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| /third_party/libdrm/tests/amdgpu/ |
| D | vce_tests.c | 56 struct amdgpu_vce_bo cpb; member
373 ib_cpu[len + 2] = enc->cpb.addr >> 32; in amdgpu_cs_vce_encode_idr()
374 ib_cpu[len + 3] = enc->cpb.addr; in amdgpu_cs_vce_encode_idr()
425 ib_cpu[len + 2] = enc->cpb.addr >> 32; in amdgpu_cs_vce_encode_p()
426 ib_cpu[len + 3] = enc->cpb.addr; in amdgpu_cs_vce_encode_p()
506 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_cs_vce_encode()
507 resources[num_resources++] = enc.cpb.handle; in amdgpu_cs_vce_encode()
564 free_resource(&enc.cpb); in amdgpu_cs_vce_encode()
588 ib_cpu[len + 2] = enc->cpb.addr >> 32; in amdgpu_cs_vce_mv()
589 ib_cpu[len + 3] = enc->cpb.addr; in amdgpu_cs_vce_mv()
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| D | uvd_enc_tests.c | 55 struct amdgpu_uvd_enc_bo cpb; member
345 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_cs_uvd_enc_encode()
346 resources[num_resources++] = enc.cpb.handle; in amdgpu_cs_uvd_enc_encode()
394 ib_cpu[len++] = enc.cpb.addr >> 32; in amdgpu_cs_uvd_enc_encode()
395 ib_cpu[len++] = enc.cpb.addr; in amdgpu_cs_uvd_enc_encode()
462 free_resource(&enc.cpb); in amdgpu_cs_uvd_enc_encode()
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| /third_party/ffmpeg/libavformat/ |
| D | dump.c | 325 const AVCPBProperties *cpb = (const AVCPBProperties *)sd->data; in dump_cpb() local
327 if (sd->size < sizeof(*cpb)) { in dump_cpb()
334 cpb->max_bitrate, cpb->min_bitrate, cpb->avg_bitrate, in dump_cpb()
335 cpb->buffer_size); in dump_cpb()
336 if (cpb->vbv_delay == UINT64_MAX) in dump_cpb()
339 av_log(ctx, AV_LOG_INFO, "vbv_delay: %"PRIu64"", cpb->vbv_delay); in dump_cpb()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | radeon_vce_50.c | 89 RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo in encode()
101 enc->cpb.res->buf->size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2; in encode()
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| D | radeon_uvd_enc.c | 237 si_vid_destroy_buffer(&enc->cpb); in radeon_uvd_enc_destroy()
334 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { in radeon_uvd_create_encoder()
346 si_vid_destroy_buffer(&enc->cpb); in radeon_uvd_create_encoder()
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| D | radeon_vcn_enc_4_0.c | 119 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); in radeon_enc_ctx()
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| D | radeon_vce.c | 250 si_vid_destroy_buffer(&enc->cpb); in rvce_destroy()
466 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { in si_vce_create_encoder()
507 si_vid_destroy_buffer(&enc->cpb); in si_vce_create_encoder()
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| D | radeon_vce_40_2_2.c | 294 RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0x0); // encodeContextAddressHi/Lo in encode()
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| D | radeon_vcn_enc.c | 382 si_vid_destroy_buffer(&enc->cpb); in radeon_enc_destroy()
515 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { in radeon_create_encoder()
534 si_vid_destroy_buffer(&enc->cpb); in radeon_create_encoder()
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| D | radeon_uvd_enc.h | 413 struct rvid_buffer cpb; member
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| D | radeon_vce_52.c | 232 RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo in encode()
244 enc->cpb.res->buf->size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2; in encode()
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| D | radeon_vce.h | 408 struct rvid_buffer cpb; member
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| D | radeon_vcn_enc.h | 566 struct rvid_buffer cpb; member
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| D | radeon_uvd_enc_1_1.c | 770 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); in radeon_uvd_enc_ctx()
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| D | radeon_vcn_enc_1_2.c | 1059 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); in radeon_enc_ctx()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | radeon_vce.c | 258 rvid_destroy_buffer(&enc->cpb); in rvce_destroy()
464 if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { in rvce_create_encoder()
482 rvid_destroy_buffer(&enc->cpb); in rvce_create_encoder()
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| D | radeon_vce.h | 406 struct rvid_buffer cpb; member
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| /third_party/ltp/testcases/kernel/controllers/cpuset/cpuset_lib/ |
| D | cpuinfo.c | 434 struct cpuset *cpb = cpusets[j]; in partition_domains() local
439 cpuset_getcpus(cpb, cpusb); in partition_domains()
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| /third_party/toybox/toys/pending/ |
| D | bc.c | 1562 BcNum cpa, cpb; in bc_num_m() local
1571 bc_num_createCopy(&cpb, b); in bc_num_m()
1573 cpa.neg = cpb.neg = 0; in bc_num_m()
1577 s = bc_num_shift(&cpb, maxrdx); in bc_num_m()
1579 s = bc_num_k(&cpa, &cpb, c); in bc_num_m()
1594 bc_num_free(&cpb); in bc_num_m()
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| /third_party/mesa3d/src/intel/vulkan/ |
| D | genX_cmd_buffer.c | 6422 device->isl_dev.cpb.size / 4); in cmd_buffer_emit_cps_control_buffer()
6433 dw + device->isl_dev.cpb.offset / 4, in cmd_buffer_emit_cps_control_buffer()
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| /third_party/astc-encoder/Test/Images/HDRIHaven/HDR-RGB/ |
| D | hdr-rgb-arboretum.hdr | 539 …����ހ��r�k}ndz[b}XMkP^d�����WMvFoec�fMwO}VIZ[\d���\�ލ�Ξ��v=x]{Wh|m�zP�c{\cpb����Ni������DŽ~�z�V�…
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