Searched refs:display_dcc_offset (Results 1 – 13 of 13) sorted by relevance
127 _mesa_sha1_update(&ctx, &surf->display_dcc_offset, sizeof(surf->display_dcc_offset)); in generate_hash()153 if (surf->display_dcc_offset) { in generate_hash()188 if (surf->display_dcc_offset) { in generate_hash()290 assert(surf.display_dcc_offset == expected_offset); in test_modifier()294 assert(!surf.display_dcc_offset); in test_modifier()
2510 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0; in ac_compute_surface()2539 …surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment… in ac_compute_surface()2540 surf->total_size = surf->display_dcc_offset + surf->u.gfx9.color.display_dcc_size; in ac_compute_surface()2558 surf->display_dcc_offset = 0; in ac_surface_zero_dcc_fields()2668 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset; in ac_surface_get_bo_metadata()2948 if (surf->display_dcc_offset) in ac_surface_override_offset_stride()2949 surf->display_dcc_offset += offset; in ac_surface_override_offset_stride()2957 else if (surf->display_dcc_offset) in ac_surface_get_nplanes()2980 return surf->display_dcc_offset ? in ac_surface_get_plane_offset()2981 surf->display_dcc_offset : surf->meta_offset; in ac_surface_get_plane_offset()[all …]
382 uint64_t display_dcc_offset; member
781 assert(tex->surface.display_dcc_offset && tex->surface.display_dcc_offset <= UINT_MAX); in si_retile_dcc()782 assert(tex->surface.display_dcc_offset < tex->surface.meta_offset); in si_retile_dcc()787 sb.buffer_offset = tex->surface.display_dcc_offset; in si_retile_dcc()790 sctx->cs_user_data[0] = tex->surface.meta_offset - tex->surface.display_dcc_offset; in si_retile_dcc()
1130 if (tex->surface.display_dcc_offset && !(surface->flags & RADEON_SURF_IMPORTED)) { in si_texture_create_object()1134 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.display_dcc_offset, in si_texture_create_object()
1292 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) { in si_flush_resource()
864 if (tex->surface.display_dcc_offset && view->access & PIPE_IMAGE_ACCESS_WRITE) { in si_set_shader_image()
2895 if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty) in si_mark_display_dcc_dirty()
230 .offset = image->planes[0].surface.display_dcc_offset, in radv_retile_dcc()
1379 (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset); in radv_init_metadata()
9447 return image->planes[0].surface.display_dcc_offset && in radv_image_need_retile()9448 image->planes[0].surface.display_dcc_offset != image->planes[0].surface.meta_offset; in radv_image_need_retile()
2340 - radeonsi: remove the "display_dcc_offset == 0" assertion
3236 - radeonsi: use display_dcc_offset for setting displayable_dcc_cb_mask