Home
last modified time | relevance | path

Searched refs:getInstr (Results 1 – 25 of 66) sorted by relevance

123

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp146 MachineInstr &MI1 = *SU.getInstr(); in apply()
155 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
183 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
187 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
207 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
210 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
231 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
273 MachineInstr &L0 = *S0.getInstr(); in apply()
286 MachineInstr &L1 = *S1.getInstr(); in apply()
321 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
[all …]
DHexagonMachineScheduler.cpp74 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
181 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
308 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
[all …]
DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
109 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
DHexagonVLIWPacketizer.cpp416 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
510 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
511 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
512 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
667 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
753 MachineInstr &TempMI = *TempSU->getInstr(); in canPromoteToNewValueStore()
766 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
820 MachineInstr &PacketMI = *PacketSU->getInstr(); in canPromoteToNewValue()
853 const MachineInstr &PI = *PacketSU->getInstr(); in canPromoteToDotNew()
1312 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
[all …]
DHexagonISelLoweringHVX.cpp483 SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
484 SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
533 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in createHvxPrefixPred()
703 return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG); in extractHvxElementPred()
872 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
996 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in insertHvxSubvectorPred()
998 ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG); in insertHvxSubvectorPred()
1293 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMul()
1308 return getInstr(Hexagon::V6_vmpyih, dl, ResTy, {Vs, Vt}, DAG); in LowerHvxMul()
1315 SDValue T0 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG); in LowerHvxMul()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/
DDebugHandlerBase.cpp231 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
234 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
235 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
236 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
241 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
246 Pred.getInstr()->getDebugExpression()); in beginFunction()
253 if (IsDescribedByReg(I->getInstr())) in beginFunction()
255 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
262 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
264 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
DDbgEntityHistoryCalculator.cpp62 Entries.back().getInstr()->isIdenticalTo(MI)) { in startDbgValue()
64 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
78 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
147 if (isDescribedByReg(*Entry.getInstr()) == RegNo) { in clobberRegEntries()
174 const MachineInstr &DV = *Entry.getInstr(); in handleNewDebugValue()
366 dbgs() << " Instr: " << *Entry.getInstr(); in dump()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCMachineScheduler.cpp31 if (isADDIInstr(*FirstCand.SU->getInstr()) && in biasAddiLoadCandidate()
32 SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
36 if (FirstCand.SU->getInstr()->mayLoad() && in biasAddiLoadCandidate()
37 isADDIInstr(*SecondCand.SU->getInstr())) { in biasAddiLoadCandidate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp161 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
162 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
195 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
220 MachineInstr *MI = SU->getInstr(); in getAluKind()
294 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
323 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
325 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
394 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
443 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
DGCNDPPCombine.cpp209 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
231 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
241 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
242 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
257 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
260 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
261 return DPPInst.getInstr(); in createDPPInst()
442 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
DSIMachineScheduler.cpp271 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
338 RPTracker.setPos(SU->getInstr()); in initRegPressure()
419 TopRPTracker.setPos(SU->getInstr()); in schedule()
1145 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1169 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr())) in colorExports()
1354 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1383 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1834 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1844 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1865 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
[all …]
DAMDGPUSubtarget.cpp725 MachineInstr *SrcI = Src->getInstr(); in adjustSchedDependency()
726 MachineInstr *DstI = Dst->getInstr(); in adjustSchedDependency()
769 MachineInstr &MI2 = *SU.getInstr(); in apply()
779 MachineInstr &MI1 = *SUa->getInstr(); in apply()
812 const MachineInstr *MI = SU->getInstr(); in isSALU()
817 const MachineInstr *MI = SU->getInstr(); in isVALU()
900 MachineInstr &MAI = *SU.getInstr(); in apply()
DGCNIterativeScheduler.cpp52 return SU->getInstr(); in getMachineInstr()
55 return SU.getInstr(); in getMachineInstr()
346 Res.push_back(SU->getInstr()); in detachSchedule()
348 return P.second == SU->getInstr(); in detachSchedule()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
262 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
265 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); in addPhysRegDataDeps()
270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
277 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle())) in addPhysRegDataDeps()
290 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
313 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
319 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
394 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
[all …]
DMachinePipeliner.cpp536 OrderedInsts.push_back(SU->getInstr()); in schedule()
537 Cycles[SU->getInstr()] = Cycle; in schedule()
538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
665 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
690 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
765 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
821 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
823 if (I.getInstr()->isPHI()) { in updatePhiDependences()
846 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
851 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
[all …]
DMacroFusion.cpp94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
161 if (DAG->ExitSU.getInstr()) in apply()
169 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
188 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
DSlotIndexes.cpp124 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
137 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
216 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
254 if (itr->getInstr()) { in dump()
255 dbgs() << *itr->getInstr(); in dump()
DMachineScheduler.cpp782 MachineInstr *MI = SU->getInstr(); in schedule()
932 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1123 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); in updatePressureDiffs()
1152 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1157 << *SU->getInstr(); in updatePressureDiffs()
1168 if (EntrySU.getInstr() != nullptr) in dump()
1177 if (SchedModel.mustBeginGroup(SU.getInstr()) && in dump()
1178 SchedModel.mustEndGroup(SU.getInstr())) in dump()
1184 if (ExitSU.getInstr() != nullptr) in dump()
1349 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp37 MachineInstr *MI = SU->getInstr(); in getHazardType()
82 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DSlotIndexes.h53 MachineInstr* getInstr() const { return mi; } in getInstr() function
402 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
411 if (I->getInstr())
592 assert(miEntry->getInstr() == &MI &&
DScheduleDAG.h373 MachineInstr *getInstr() const { in getInstr() function
387 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0); in addPredBarrier()
582 if (SU->isInstr()) return &SU->getInstr()->getDesc(); in getInstrDesc()
DMachinePipeliner.h249 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
259 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti) in getDistance()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyFixIrreducibleControlFlow.cpp372 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; in makeSingleEntryLoop()
467 MIB.addMBB(MIB.getInstr() in makeSingleEntryLoop()
468 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1) in makeSingleEntryLoop()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp437 .getInstr(); in loadImmediate()
441 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); in loadImmediate()
449 .getInstr(); in loadImmediate()

123