| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 166 assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type"); in buildDynStackAlloc()
168 Res.addDefToMIB(*getMRI(), MIB); in buildDynStackAlloc()
176 assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type"); in buildFrameIndex()
178 Res.addDefToMIB(*getMRI(), MIB); in buildFrameIndex()
185 assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type"); in buildGlobalValue()
186 assert(Res.getLLTTy(*getMRI()).getAddressSpace() == in buildGlobalValue()
191 Res.addDefToMIB(*getMRI(), MIB); in buildGlobalValue()
217 assert(Res.getLLTTy(*getMRI()).isPointer() && in buildPtrAdd()
218 Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch"); in buildPtrAdd()
219 assert(Op1.getLLTTy(*getMRI()).isScalar() && "invalid offset type"); in buildPtrAdd()
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| D | CSEMIRBuilder.cpp | 65 B.addNodeIDRegType(Op.getLLTTy(*getMRI())); in profileDstOp()
161 SrcOps[1].getReg(), *getMRI())) in buildInstr()
172 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI())) in buildInstr()
190 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); in buildInstr()
211 LLT Ty = Res.getLLTTy(*getMRI()); in buildConstant()
216 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); in buildConstant()
238 LLT Ty = Res.getLLTTy(*getMRI()); in buildFConstant()
243 GISelInstProfileBuilder ProfBuilder(ID, *getMRI()); in buildFConstant()
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| D | CallLowering.cpp | 135 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); in packRegs()
237 MIRBuilder.getMRI()->createGenericVirtualRegister(NewLLT); in handleAssignments()
328 MIRBuilder.getMRI()->createGenericVirtualRegister(VATy); in handleAssignments()
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| D | RegisterBankInfo.cpp | 441 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyDefaultMapping()
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| D | CombinerHelper.cpp | 936 MachineRegisterInfo &MRI = *MIB.getMRI(); in getMemsetValue()
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| D | LegalizerHelper.cpp | 4433 const LLT Ty = Dst.getLLTTy(*B.getMRI()); in SwapN()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | ConstantFoldingMIRBuilder.h | 53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
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| D | MachineIRBuilder.h | 271 MachineRegisterInfo *getMRI() { return State.MRI; } in getMRI() function
272 const MachineRegisterInfo *getMRI() const { return State.MRI; } in getMRI() function
1342 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); in buildNot()
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| D | RegisterBankInfo.h | 334 MachineRegisterInfo &getMRI() const { return MRI; } in getMRI() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIPeepholeSDWA.cpp | 128 MachineRegisterInfo *getMRI() const { in getMRI() function in __anon751e5d270111::SDWAOperand
358 MachineOperand *PotentialMO = findSingleRegUse(getReplacedOperand(), getMRI()); in potentialToConvert()
442 MachineRegisterInfo *MRI = getMRI(); in potentialToConvert()
496 getMRI()->clearKillFlags(MO.getReg()); in convertToSDWA()
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| D | SIMachineScheduler.h | 458 MachineRegisterInfo *getMRI() { return &MRI; } in getMRI() function
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| D | SIMachineScheduler.cpp | 330 MachineRegisterInfo *MRI = DAG->getMRI(); in initRegPressure()
1749 PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg); in checkRegUsageImpact()
1759 PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg); in checkRegUsageImpact()
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| D | AMDGPURegisterBankInfo.cpp | 681 MachineRegisterInfo *MRI = B.getMRI(); in split64BitValueForMapping()
1242 B.getMRI()->setRegBank(Cmp.getReg(0), AMDGPU::SGPRRegBank); in lowerScalarMinMax()
1304 std::tie(BaseReg, ImmOffset) = getBaseWithConstantOffset(*B.getMRI(), in splitBufferOffsets()
1360 MachineRegisterInfo &MRI = *B.getMRI(); in selectStoreIntrinsic()
1437 MachineRegisterInfo &MRI = *B.getMRI(); in buildVCopy()
1472 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingImpl()
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| D | AMDGPULegalizerInfo.cpp | 1656 B.getMRI()->createGenericVirtualRegister(ConstPtrTy); in buildPCRelGlobalAddress()
1667 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
1848 MachineRegisterInfo &MRI = *B.getMRI(); in loadInputValue()
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| D | AMDGPUCallLowering.cpp | 519 MachineRegisterInfo &MRI = *B.getMRI(); in packSplitRegsToOrigType()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 307 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.cpp | 669 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingImpl()
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| D | MipsCallLowering.cpp | 109 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| D | MipsInstructionSelector.cpp | 162 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 409 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 2903 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in emitExtractVectorElt()
3476 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptSelect()
3576 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in tryFoldIntegerCompare()
3678 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptVectorDup()
3870 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in emitLaneInsert()
4772 MachineRegisterInfo &MRI = *MIB.getMRI(); in narrowExtendRegIfNeeded()
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| D | AArch64CallLowering.cpp | 113 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1205 const MCRegisterInfo *getMRI() const { in getMRI() function in __anon6f3692530111::AMDGPUAsmParser
1638 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2957 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); in validateMIMGDataSize()
2998 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()
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