| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
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| D | HexagonVLIWPacketizer.cpp | 708 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore()
720 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore()
1423 RC = HRI->getMinimalPhysRegClass(DepReg); in isLegalToPacketizeTogether()
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| D | HexagonFrameLowering.cpp | 1270 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRSpillsInBlock()
1334 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRRestoresInBlock()
1550 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); in assignCalleeSavedSpillSlots()
1562 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); in assignCalleeSavedSpillSlots()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerSGPRSpills.cpp | 103 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSaves()
136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRRestores()
209 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegs()
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| D | GCNRegBankReassign.cpp | 281 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getPhysRegBank()
308 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getRegBankMask()
442 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg); in isReassignable()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 88 return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT()); in getRegBank()
101 RegisterBankInfo::getMinimalPhysRegClass(Register Reg, in getMinimalPhysRegClass() function in RegisterBankInfo
107 const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg); in getMinimalPhysRegClass()
502 auto *RC = &getMinimalPhysRegClass(Reg, TRI); in getSizeInBits()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
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| D | WebAssemblyInstrInfo.cpp | 66 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
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| D | MipsSEFrameLowering.cpp | 262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); in expandCopyACC()
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 812 if (TRI->getMinimalPhysRegClass(OriginalReg) == in mergePairedInsns()
813 TRI->getMinimalPhysRegClass(SubOrSuper)) in mergePairedInsns()
1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef()
1354 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1368 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1411 return C == TRI->getMinimalPhysRegClass(SubOrSuper); in tryToFindRegisterToRename()
1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 190 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
479 RC = getMinimalPhysRegClass(Reg); in getRegSizeInBits()
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| D | StackMaps.cpp | 153 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
249 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg)); in createLiveOutReg()
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| D | PrologEpilogInserter.cpp | 419 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
552 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSaves()
579 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRRestores()
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| D | MachineCopyPropagation.cpp | 433 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg()); in isForwardableRegClassCopy()
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| D | AggressiveAntiDepBreaker.cpp | 630 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 111 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in PrintAsmOperand()
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| D | AVRFrameLowering.cpp | 254 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
292 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 440 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
468 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 439 getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 136 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); in addMachineReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 312 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 159 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 574 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 2039 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); in assignCalleeSavedSpillSlots()
2122 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); in spillCalleeSavedRegisters()
2201 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); in restoreCalleeSavedRegisters()
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