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Searched refs:getReg (Results 1 – 25 of 521) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86InstComments.cpp217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
240 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
270 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
275 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
276 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
281 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
286 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
287 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
292 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
297 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp121 RegsToInvalidate.insert(MI->getOperand(0).getReg()); in invalidateRegister()
122 RegsToInvalidate.insert(MI->getOperand(1).getReg()); in invalidateRegister()
144 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI); in clobberRegister()
155 Register Def = MI->getOperand(0).getReg(); in trackCopy()
156 Register Src = MI->getOperand(1).getReg(); in trackCopy()
202 !TRI.isSubRegisterEq(AvailCopy->getOperand(1).getReg(), Reg)) in findAvailBackwardCopy()
205 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailBackwardCopy()
206 Register AvailDef = AvailCopy->getOperand(0).getReg(); in findAvailBackwardCopy()
226 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg)) in findAvailCopy()
231 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailCopy()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp67 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
68 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
82 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
83 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
94 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
104 Register Reg = Op.getReg(); in applyBank()
250 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
255 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
427 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
453 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
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DSIFixSGPRCopies.cpp158 !Register::isVirtualRegister(MI.getOperand(i).getReg())) in hasVectorOperands()
161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
171 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses()
172 Register SrcReg = Copy.getOperand(1).getReg(); in getCopyRegClasses()
207 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy()
208 Register SrcReg = Src.getReg(); in tryChangeVGPRtoSGPRinCopy()
246 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence()
258 if (Register::isPhysicalRegister(CopyUse.getOperand(0).getReg())) in foldVGPRCopyIntoRegSequence()
285 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg()); in foldVGPRCopyIntoRegSequence()
289 Register SrcReg = MI.getOperand(I).getReg(); in foldVGPRCopyIntoRegSequence()
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DSIShrinkInstructions.cpp80 Register Reg = Src0.getReg(); in foldImmediates()
254 unsigned Vgpr = TRI.getHWRegIndex(Op.getReg()); in shrinkMIMG()
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) { in shrinkScalarLogicOp()
364 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
365 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
375 MI.getOperand(2).ChangeToRegister(Dest->getReg(), false); in shrinkScalarLogicOp()
397 Register::isPhysicalRegister(MO.getReg())) { in instAccessReg()
398 if (TRI.regsOverlap(Reg, MO.getReg())) in instAccessReg()
400 } else if (MO.getReg() == Reg && Register::isVirtualRegister(Reg)) { in instAccessReg()
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DAMDGPUInstructionSelector.cpp98 Register DstReg = Dst.getReg(); in selectCOPY()
99 Register SrcReg = Src.getReg(); in selectCOPY()
161 if (Register::isPhysicalRegister(MO.getReg())) in selectCOPY()
168 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
174 const Register DefReg = I.getOperand(0).getReg(); in selectPHI()
214 Register Reg = MO.getReg(); in getSubOperand64()
255 Register DstReg = Dst.getReg(); in selectG_AND_OR_XOR()
269 if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg())) in selectG_AND_OR_XOR()
270 MRI->setRegClass(Src0.getReg(), RC); in selectG_AND_OR_XOR()
271 if (Src1.isUndef() && !MRI->getRegClassOrNull(Src1.getReg())) in selectG_AND_OR_XOR()
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DAMDGPULegalizerInfo.cpp1216 .addUse(ShiftAmt.getReg(0)); in getSegmentAperture()
1258 Register Dst = MI.getOperand(0).getReg(); in legalizeAddrSpaceCast()
1259 Register Src = MI.getOperand(1).getReg(); in legalizeAddrSpaceCast()
1295 B.buildMerge(Dst, {Src, HighAddr.getReg(0)}); in legalizeAddrSpaceCast()
1314 B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0)); in legalizeAddrSpaceCast()
1315 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1337 B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1350 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0)); in legalizeAddrSpaceCast()
1361 Register Src = MI.getOperand(1).getReg(); in legalizeFrint()
1379 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
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DSIOptimizeExecMasking.cpp69 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
70 return MI.getOperand(0).getReg(); in isCopyFromExec()
85 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
87 return MI.getOperand(1).getReg(); in isCopyToExec()
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
112 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
115 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
128 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp386 Args.push_back({MI.getOperand(i).getReg(), OpType}); in simpleLibcall()
387 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, in simpleLibcall()
400 Register Reg = MI.getOperand(i).getReg(); in createMemLibcall()
485 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, in conversionLibcall()
486 {{MI.getOperand(1).getReg(), FromType}}); in conversionLibcall()
491 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); in libcall()
539 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
540 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in libcall()
551 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
552 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in libcall()
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DGISelKnownBits.cpp66 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
134 if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() && in computeKnownBitsImpl()
136 MRI.getType(Src.getReg()).isValid()) { in computeKnownBitsImpl()
138 computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth); in computeKnownBitsImpl()
158 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
163 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
170 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
172 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
184 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
197 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
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DCombinerHelper.cpp75 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
76 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
109 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
110 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
136 Register Reg = MO.getReg(); in matchCombineConcatVectors()
145 Ops.push_back(BuildVecMO.getReg()); in matchCombineConcatVectors()
154 assert(MRI.getType(Undef->getOperand(0).getReg()) == in matchCombineConcatVectors()
161 Ops.push_back(Undef->getOperand(0).getReg()); in matchCombineConcatVectors()
174 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
205 LLT DstType = MRI.getType(MI.getOperand(0).getReg()); in matchCombineShuffleVector()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp110 printRegName(O, Dst.getReg()); in printInst()
112 printRegName(O, MO1.getReg()); in printInst()
115 printRegName(O, MO2.getReg()); in printInst()
132 printRegName(O, Dst.getReg()); in printInst()
134 printRegName(O, MO1.getReg()); in printInst()
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
164 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
169 printRegName(O, MI->getOperand(1).getReg()); in printInst()
179 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
193 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp434 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
452 if (!Register::isVirtualRegister(MO.getReg())) { in unsupportedBinOp()
457 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
587 const Register DstReg = I.getOperand(0).getReg(); in isValidCopy()
588 const Register SrcReg = I.getOperand(1).getReg(); in isValidCopy()
628 .addReg(Copy.getReg(0), 0, SubReg); in selectSubregisterCopy()
630 RegOp.setReg(SubRegCopy.getReg(0)); in selectSubregisterCopy()
634 if (!Register::isPhysicalRegister(I.getOperand(0).getReg())) in selectSubregisterCopy()
635 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in selectSubregisterCopy()
648 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
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DAArch64RegisterBankInfo.cpp280 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
301 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
337 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
429 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
445 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg()); in getSameKindOfOperandsMapping()
476 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
548 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
549 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
559 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping()
560 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp202 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
203 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
220 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
221 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
261 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
262 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp235 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
270 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
280 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
293 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
300 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
314 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
315 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
323 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
324 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
333 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h54 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
55 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
103 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
104 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
147 Register DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
148 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineSExt()
174 Register DstReg = MI.getOperand(0).getReg(); in tryCombineTrunc()
175 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineTrunc()
204 MI.getOperand(1).getReg(), MRI)) { in tryFoldImplicitDef()
206 Register DstReg = MI.getOperand(0).getReg(); in tryFoldImplicitDef()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp153 Register Reg = Op->getReg(); in getVRegDefOrNull()
346 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); in simplifyCode()
348 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); in simplifyCode()
368 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
382 MI.getOperand(0).getReg()) in simplifyCode()
391 unsigned DefReg1 = DefMI->getOperand(1).getReg(); in simplifyCode()
392 unsigned DefReg2 = DefMI->getOperand(2).getReg(); in simplifyCode()
412 MI.getOperand(0).getReg()) in simplifyCode()
436 MI.getOperand(0).getReg()) in simplifyCode()
446 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
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DPPCVSXCopy.cpp94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
123 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
261 Register T = MO.getReg(); in partitionRegisters()
375 Register Rs = MI->getOperand(1).getReg(); in profit()
376 Register Rt = MI->getOperand(2).getReg(); in profit()
443 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
502 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
510 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
538 Register R = MD.getReg(); in collectIndRegsForLoop()
554 Register T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
606 Register R = Op.getReg(); in createHalfInstr()
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DHexagonInstrInfo.cpp196 Register Reg = MO.getReg(); in parseOperands()
201 Uses.push_back(MO.getReg()); in parseOperands()
204 Defs.push_back(MO.getReg()); in parseOperands()
261 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
275 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
309 return MI.getOperand(2).getReg(); in isStoreToStackSlot()
327 return MI.getOperand(3).getReg(); in isStoreToStackSlot()
635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). in insertBranch()
636 addReg(Cond[2].getReg(), Flags2).addMBB(TBB); in insertBranch()
638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). in insertBranch()
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DHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); in runOnMachineFunction()
140 Register SrcReg = Src.getReg(); in runOnMachineFunction()
160 Register DstReg = Dst.getReg(); in runOnMachineFunction()
161 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
177 Register DstReg = Dst.getReg(); in runOnMachineFunction()
178 Register SrcReg = Src1.getReg(); in runOnMachineFunction()
188 Register DstReg = Dst.getReg(); in runOnMachineFunction()
189 Register SrcReg = Src.getReg(); in runOnMachineFunction()
211 Register DstReg = Dst.getReg(); in runOnMachineFunction()
212 Register SrcReg = Src.getReg(); in runOnMachineFunction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp580 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { in getReg() function
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) in detectLuiAddiGlobal()
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); in detectLuiAddiGlobal()
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) in detectLuiAddiGlobal()
110 MRI->replaceRegWith(Tail.getOperand(0).getReg(), in foldOffset()
111 LoADDI.getOperand(0).getReg()); in foldOffset()
138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset()
139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset()
155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); in matchLargeOffset()
159 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg())) in matchLargeOffset()
181 Register DestReg = LoADDI.getOperand(0).getReg(); in detectAndFoldOffset()
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