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Searched refs:getRegClass (Results 1 – 25 of 191) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
165 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
170 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
DWebAssemblyInstrInfo.cpp65 ? MRI.getRegClass(DestReg) in copyPhysReg()
197 bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) == in insertBranch()
228 MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass) in reverseBranchCondition()
DWebAssemblyExplicitLocals.cpp243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
278 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
353 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
384 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
DWebAssemblyRegColoring.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC) in runOnMachineFunction()
DWebAssemblyMemIntrinsicResults.cpp171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg)) in optimizeCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
175 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
182 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
247 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
677 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
678 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
679 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
787 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode()
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DSIFixupVectorISel.cpp127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg()); in findSRegBaseAndIndex()
137 BaseRC = MRI.getRegClass(BaseReg); in findSRegBaseAndIndex()
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg))) in findSRegBaseAndIndex()
DSIInstrInfo.cpp488 ? MRI.getRegClass(Reg) in shouldClusterMemOps()
763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate()
829 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in insertVectorSelect()
830 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && in insertVectorSelect()
2135 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
2136 assert(MRI.getRegClass(FalseReg) == RC); in canInsertSelect()
2149 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
2150 assert(MRI.getRegClass(FalseReg) == RC); in canInsertSelect()
2177 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); in insertSelect()
2383 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
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DSIRegisterInfo.h135 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
141 RC = MRI.getRegClass(Reg); in isSGPRReg()
282 const TargetRegisterClass *getRegClass(unsigned RCID) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp127 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
128 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass() function in X86InstructionSelector
197 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
200 return getRegClass(Ty, RegBank); in getRegClass()
248 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
278 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
727 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
728 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
809 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectZext()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
133 MRI.getRegClass(AddendSrcReg)) in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
238 MRI.getRegClass(OldFMAReg))) in processBlock()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
161 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
204 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
379 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF)) in AddOperand()
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
517 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
574 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
615 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp139 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
336 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
435 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
479 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
481 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
DHexagonSplitDouble.cpp228 if (MRI->getRegClass(R) == DoubleRC) in partitionRegisters()
266 if (MRI->getRegClass(T) != DoubleRC) in partitionRegisters()
503 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass); in collectIndRegsForLoop()
517 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC) in collectIndRegsForLoop()
519 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC) in collectIndRegsForLoop()
539 if (MRI->getRegClass(R) == DoubleRC) in collectIndRegsForLoop()
610 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) { in createHalfInstr()
676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); in splitMemRef()
1006 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
1110 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg()) in collapseRegPairs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
DPeepholeOptimizer.cpp474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
571 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
731 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1425 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
1960 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) || in getNextSourceFromInsertSubreg()
DRegAllocBase.cpp107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
DTargetRegisterInfo.cpp157 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
179 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
244 return TRI->getRegClass(I + countTrailingZeros(Common)); in firstCommonClass()
488 RC = MRI.getRegClass(Reg); in getRegSizeInBits()
DModuloSchedule.cpp548 const TargetRegisterClass *RC = MRI.getRegClass(Def); in generateExistingPhis()
664 const TargetRegisterClass *RC = MRI.getRegClass(Def); in generatePhis()
812 SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def)); in splitLifetimes()
1033 const TargetRegisterClass *RC = MRI.getRegClass(reg); in updateInstruction()
1184 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1232 MRI.getRegClass(MI.getOperand(0).getReg())); in EliminateDeadPhis()
1428 LoopReg = phi(LoopReg, *DefaultI++, MRI.getRegClass(Reg)); in remapUse()
1436 auto RC = MRI.getRegClass(Reg); in remapUse()
1476 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue())); in phi()
1483 RC = MRI.getRegClass(LoopReg); in phi()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg()); in getRC32()
122 MRI->getRegClass(VirtReg)); in getRegAllocationHints()
136 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) { in getRegAllocationHints()
171 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass) in getRegAllocationHints()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1268 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || in printVectorList()
1269 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || in printVectorList()
1270 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) in printVectorList()
1272 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || in printVectorList()
1273 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || in printVectorList()
1274 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) in printVectorList()
1276 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || in printVectorList()
1277 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || in printVectorList()
1278 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) in printVectorList()
1291 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { in printVectorList()
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