Searched refs:getRegClassForReg (Results 1 – 7 of 7) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 207 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
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| D | SIRegisterInfo.cpp | 637 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1679 SIRegisterInfo::getRegClassForReg(const MachineRegisterInfo &MRI, in getRegClassForReg() function in SIRegisterInfo
1689 const TargetRegisterClass * RC = getRegClassForReg(MRI, Reg); in isVGPR()
1696 const TargetRegisterClass * RC = getRegClassForReg(MRI, Reg); in isAGPR()
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| D | GCNRegBankReassign.cpp | 369 if (TRI->hasAGPRs(TRI->getRegClassForReg(*MRI, R))) in analyzeInst()
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| D | SIFixSGPRCopies.cpp | 818 TRI->getRegClassForReg(*MRI, SrcReg); in processPHINode()
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| D | SIInstrInfo.cpp | 3327 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
4291 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
5076 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { in moveToVALU()
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| D | AMDGPUInstructionSelector.cpp | 1438 const TargetRegisterClass *RC = TRI.getRegClassForReg(*MRI, DstReg); in selectG_CONSTANT()
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| D | SIISelLowering.cpp | 10466 auto *RC = TRI->getRegClassForReg(MRI, Op.getReg()); in AdjustInstrPostInstrSelection()
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