| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstX8664.cpp | 250 assert(RegX8664::getEncodedGPR(Eax->getRegNum()) == Encoded_rAX); in InstX86Cmpxchg()
260 assert(Edx->getRegNum() == RegisterSet::Reg_edx); in InstX86Cmpxchg8b()
261 assert(Eax->getRegNum() == RegisterSet::Reg_eax); in InstX86Cmpxchg8b()
262 assert(Ecx->getRegNum() == RegisterSet::Reg_ecx); in InstX86Cmpxchg8b()
263 assert(Ebx->getRegNum() == RegisterSet::Reg_ebx); in InstX86Cmpxchg8b()
533 Asm->jmp(RegX8664::getEncodedGPR(Var->getRegNum())); in emitIAS()
592 Asm->call(RegX8664::getEncodedGPR(Var->getRegNum())); in emitIAS()
648 GPRRegister VarReg = RegX8664::getEncodedGPR(Var->getRegNum()); in emitIASOpTyGPR()
669 GPRRegister VarReg = VarCanBeByte ? RegX8664::getEncodedGPR(Var->getRegNum()) in emitIASRegOpTyGPR()
670 : RegX8664::getEncodedGPR(Var->getRegNum()); in emitIASRegOpTyGPR()
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| D | IceInstX8632.cpp | 262 assert(RegX8632::getEncodedGPR(Eax->getRegNum()) == Encoded_rAX); in InstX86Cmpxchg()
272 assert(Edx->getRegNum() == RegisterSet::Reg_edx); in InstX86Cmpxchg8b()
273 assert(Eax->getRegNum() == RegisterSet::Reg_eax); in InstX86Cmpxchg8b()
274 assert(Ecx->getRegNum() == RegisterSet::Reg_ecx); in InstX86Cmpxchg8b()
275 assert(Ebx->getRegNum() == RegisterSet::Reg_ebx); in InstX86Cmpxchg8b()
546 Asm->jmp(RegX8632::getEncodedGPR(Var->getRegNum())); in emitIAS()
605 Asm->call(RegX8632::getEncodedGPR(Var->getRegNum())); in emitIAS()
661 GPRRegister VarReg = RegX8632::getEncodedGPR(Var->getRegNum()); in emitIASOpTyGPR()
682 GPRRegister VarReg = VarCanBeByte ? RegX8632::getEncodedGPR(Var->getRegNum()) in emitIASRegOpTyGPR()
683 : RegX8632::getEncodedGPR(Var->getRegNum()); in emitIASRegOpTyGPR()
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| D | IceCfgNode.cpp | 379 const auto RegNum1 = Var1->getRegNum(); in sameVarOrReg()
380 const auto RegNum2 = Var2->getRegNum(); in sameVarOrReg()
975 const auto RegNum = Var->getRegNum(); in emitRegisterUsage()
986 return unsigned(V1->getRegNum()) < unsigned(V2->getRegNum()); in emitRegisterUsage()
1013 ++LiveRegCount[Dest->getRegNum()]; in emitLiveRangesEnded()
1018 SizeT NewCount = --LiveRegCount[Var->getRegNum()]; in emitLiveRangesEnded()
1110 ++LiveRegCount[Dest->getRegNum()]; in emit()
1112 --LiveRegCount[llvm::cast<Variable>(I.getSrc(0))->getRegNum()]; in emit()
1183 << Func->getTarget()->getRegName(Var->getRegNum(), in dump()
1209 << Func->getTarget()->getRegName(Var->getRegNum(), in dump()
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| D | IceRegAlloc.cpp | 134 Var->setRegNumTmp(Var->getRegNum()); in initForGlobal()
261 Var->setRegNumTmp(Var->getRegNum()); in initForInfOnly()
313 Var->setRegNumTmp(Var->getRegNum()); in initForSecondChance()
604 *RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp() in filterFreeWithPrecoloredRanges()
621 const auto RegNum = Cur->getRegNum(); in allocatePrecoloredRegister()
796 Str << (AssignedRegNum == Item->getRegNum() ? "Reassigning " in assignFinalRegisters()
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| D | IceTargetLoweringMIPS32.cpp | 1126 Str << '$' << getRegName(Var->getRegNum(), Var->getType()); in emitVariable()
1630 if (RegMIPS32::isFPRReg(Var->getRegNum())) in addProlog()
1634 auto *PhysicalRegister = makeReg(RegType, Var->getRegNum()); in addProlog()
1754 if (RegMIPS32::isFPRReg((*RIter)->getRegNum())) in addEpilog()
1758 auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum()); in addEpilog()
1815 IceType_f32, RegMIPS32::get64PairFirstRegNum(SrcV->getRegNum())); in legalizeMovFp()
1818 IceType_f32, RegMIPS32::get64PairSecondRegNum(SrcV->getRegNum())); in legalizeMovFp()
1848 const bool IsDstGPR = RegMIPS32::isGPRReg(Dest->getRegNum()); in legalizeMov()
1849 const bool IsSrcGPR = RegMIPS32::isGPRReg(SrcR->getRegNum()); in legalizeMov()
1850 const RegNumT SRegNum = SrcR->getRegNum(); in legalizeMov()
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| D | IceInstARM32.cpp | 1363 const auto Base = BaseReg->getRegNum(); in emitSRegsAsText()
1391 return RegNumT::fixme(Before->getRegNum() + 1) == After->getRegNum(); in isAssignedConsecutiveRegisters()
1411 RegARM32::getEncodedGPR(Var->getRegNum()); in emitUsingForm()
1562 const auto SrcReg = Src->getRegNum(); in getDRegister()
1619 const auto SrcReg = Src->getRegNum(); in getSRegister()
1750 Asm->vmovqir(Dest->asType(Func, DestTy, Dest->getRegNum()), in emitIAS()
1752 Src->asType(Func, SrcTy, Src->getRegNum()), getPredicate()); in emitIAS()
2640 assert(LR->getRegNum() == RegARM32::Reg_lr); in emit()
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| D | IceTargetLoweringARM32.cpp | 397 RegNumT::fixme(RegARM32::getI64PairFirstGPRNum(Var->getRegNum())); in copyRegAllocFromInfWeightVariable64On32()
1077 Str << getRegName(Var->getRegNum(), Var->getType()); in emitVariable()
1602 Base->getRegNum() == Target->getFrameOrStackReg(); in newBaseRegister()
1659 assert(TempBaseReg->getRegNum() == Target->getReservedTmpReg()); in resetTempBaseIfClobberedBy()
1664 Dest->getRegNum() == TempBaseReg->getRegNum()) { in resetTempBaseIfClobberedBy()
1708 const int32_t ExtraOffset = (Var->getRegNum() == Target->getFrameReg()) in legalizeMov()
1713 Variable *Base = Target->getPhysicalRegister(Var->getRegNum()); in legalizeMov()
1714 Variable *T = newBaseRegister(Base, Offset, Dest->getRegNum()); in legalizeMov()
1782 const int32_t ExtraOffset = (Base->getRegNum() == Target->getFrameReg()) in legalizeMemOperand()
1786 Base = Target->getPhysicalRegister(Base->getRegNum()); in legalizeMemOperand()
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| D | IceCfg.cpp | 1036 Src0Var->getRegNum(), Src0Var->getStackOffset() + Src1Imm->getValue()); in rematerializeArithmetic()
1052 Instr->getDest()->setRematerializable(Src0Var->getRegNum(), in rematerializeAssign()
1073 Dest->setRematerializable(Src0Var->getRegNum(), Src0Var->getStackOffset()); in rematerializeCast()
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| D | IceInst.cpp | 1029 if (Dest->hasReg() && Dest->getRegNum() == SrcVar->getRegNum()) { in checkForRedundantAssign()
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| D | IceOperand.h | 741 bool hasReg() const { return getRegNum().hasValue(); } in hasReg()
742 RegNumT getRegNum() const { return RegNum; } in getRegNum() function
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| D | IceInstMIPS32.cpp | 334 assert(RA->getRegNum() == RegMIPS32::Reg_RA); in emit()
519 assert(RA->getRegNum() == RegMIPS32::Reg_RA); in emitIAS()
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| D | IceOperand.cpp | 228 const auto RegNum = getRegNum(); in getRematerializableOffset()
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| D | IceAssemblerMIPS32.cpp | 127 const auto Reg = Var->getRegNum(); in getEncodedGPRegNum()
133 const auto Reg = Var->getRegNum(); in getEncodedFPRegNum()
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| D | IceAssemblerX8632.cpp | 97 SetBaseIndex(RegX8632::getEncodedGPR(Mem->getBase()->getRegNum()), in AsmAddress()
98 RegX8632::getEncodedGPR(Mem->getIndex()->getRegNum()), in AsmAddress()
101 SetBase(RegX8632::getEncodedGPR(Mem->getBase()->getRegNum()), Disp, Fixup); in AsmAddress()
103 SetIndex(RegX8632::getEncodedGPR(Mem->getIndex()->getRegNum()), in AsmAddress()
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| D | IceAssemblerX8664.cpp | 88 SetBaseIndex(RegX8664::getEncodedGPR(Mem->getBase()->getRegNum()), in AsmAddress()
89 RegX8664::getEncodedGPR(Mem->getIndex()->getRegNum()), in AsmAddress()
92 SetBase(RegX8664::getEncodedGPR(Mem->getBase()->getRegNum()), Disp, Fixup); in AsmAddress()
94 SetIndex(RegX8664::getEncodedGPR(Mem->getIndex()->getRegNum()), in AsmAddress()
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| D | IceAssemblerARM32.cpp | 180 const auto Reg = Var->getRegNum(); in getEncodedGPRegNum()
187 return RegARM32::getEncodedSReg(Var->getRegNum()); in getEncodedSRegNum()
191 return RegARM32::getEncodedDReg(Var->getRegNum()); in getEncodedDRegNum()
195 return RegARM32::getEncodedQReg(Var->getRegNum()); in getEncodedQRegNum()
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| D | IceTargetLowering.cpp | 777 RegsUsed[Var->getRegNum()] = true; in getVarStackSlotParams()
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| D | IceTargetLoweringX8632.cpp | 799 Str << "%" << getRegName(Var->getRegNum(), Var->getType()); in emitVariable()
5563 if (Var->getRegNum() == getStackReg()) in doMockBoundsCheck()
6298 SrcLegal = legalize(Src, Legal_Reg, Dest->getRegNum()); in lowerMove()
7235 assert(Slot->getRegNum().hasNoValue()); in getMemoryOperandForStackSlot()
7451 (RegNum.hasValue() && RegNum != Var->getRegNum())) { in legalize()
7881 _push_reg(ECX->getRegNum()); in emitStackProbe()
7891 _pop_reg(ECX->getRegNum()); in emitStackProbe()
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| D | IceTargetLoweringX8664.cpp | 809 Str << "%" << getRegName(Var->getRegNum(), Var->getType()); in emitVariable()
4973 if (Var->getRegNum() == getStackReg()) in doMockBoundsCheck()
5686 SrcLegal = legalize(Src, Legal_Reg, Dest->getRegNum()); in lowerMove()
6497 assert(Slot->getRegNum().hasNoValue()); in getMemoryOperandForStackSlot()
6723 (RegNum.hasValue() && RegNum != Var->getRegNum())) { in legalize()
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| D | IceTargetLoweringARM32.h | 1019 TempBaseReg->getRegNum() == Target->getReservedTmpReg()); in assertNoTempOrAssignedToIP()
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| D | IceInstX8632.h | 1136 const auto SrcReg = SrcVar->getRegNum(); in isRedundantAssign()
1137 const auto DestReg = this->Dest->getRegNum(); in isRedundantAssign()
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| D | IceInstX8664.h | 1075 const auto SrcReg = SrcVar->getRegNum(); in isRedundantAssign()
1076 const auto DestReg = this->Dest->getRegNum(); in isRedundantAssign()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2069 static bool getRegNum(StringRef Str, unsigned& Num) { in getRegNum() function
2094 if (getRegNum(RegSuffix, Num)) in isRegister()
2200 if (!getRegNum(RegSuffix, RegNum)) in ParseRegularReg()
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