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Searched refs:getSubReg (Results 1 – 25 of 131) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
846 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
849 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
892 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
929 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
934 if (MODef.getSubReg()) in getNextRewritableSource()
977 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
985 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1064 return MODef.getSubReg() == 0; in getNextRewritableSource()
[all …]
DDetectDeadLanes.cpp162 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
201 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
297 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
346 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
398 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
412 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
427 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
460 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
DCalcSpillWeights.cpp57 sub = mi->getOperand(0).getSubReg(); in copyHint()
59 hsub = mi->getOperand(1).getSubReg(); in copyHint()
61 sub = mi->getOperand(1).getSubReg(); in copyHint()
63 hsub = mi->getOperand(0).getSubReg(); in copyHint()
73 Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); in copyHint()
DTargetInstrInfo.cpp177 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
178 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
179 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl()
444 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
518 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
558 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) { in foldMemoryOperand()
897 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() && in isReallyTriviallyReMaterializableGeneric()
1234 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1260 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1285 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
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DTargetRegisterInfo.cpp271 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
310 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
319 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
329 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
330 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
DRegAllocFast.cpp768 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
770 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
859 if (!MO.getSubReg()) { in setPhysReg()
866 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register()); in setPhysReg()
897 (MO.getSubReg() && MI.readsVirtualRegister(Reg))) { in handleThroughOperands()
936 } else if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) { in handleThroughOperands()
1024 CopyDstSub = MI.getOperand(0).getSubReg(); in allocateInstruction()
1025 CopySrcSub = MI.getOperand(1).getSubReg(); in allocateInstruction()
1057 if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) in allocateInstruction()
DMachineOperand.cpp78 if (SubIdx && getSubReg()) in substVirtReg()
79 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
87 if (getSubReg()) { in substPhysReg()
88 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
283 getSubReg() == Other.getSubReg(); in isIdenticalTo()
348 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
761 if (unsigned SubReg = getSubReg()) { in print()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp35 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
36 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
39 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
40 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
118 if (MO->getSubReg()) in getRegAllocationHints()
119 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
120 if (VRRegMO->getSubReg()) in getRegAllocationHints()
121 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
224 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
230 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIFoldOperands.cpp301 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
483 SubDef && Sub->isReg() && !Sub->getSubReg() && in getRegSeqInit()
576 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
599 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
693 !UseMI->getOperand(1).getSubReg()) { in foldOperand()
699 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
835 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
867 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()
875 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
878 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
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DGCNRegBankReassign.cpp284 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
305 Reg = TRI->getSubReg(Reg, SubReg); in getRegBankMask()
311 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getRegBankMask()
374 if (Bank != -1 && R == Reg && Op.getSubReg()) { in analyzeInst()
375 unsigned LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()).getAsInteger(); in analyzeInst()
391 unsigned Mask = getRegBankMask(R, Op.getSubReg(), in analyzeInst()
395 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask)); in analyzeInst()
448 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0); in isReassignable()
DSIShrinkInstructions.cpp402 TRI.getSubRegIndexLaneMask(MO.getSubReg()); in instAccessReg()
427 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); in getSubRegForIndex()
461 unsigned Tsub = MovT.getOperand(0).getSubReg(); in matchSwap()
467 unsigned Xsub = Xop.getSubReg(); in matchSwap()
476 if (YTop.getSubReg() != Tsub) in matchSwap()
482 MovY.getOperand(1).getSubReg() != Tsub) in matchSwap()
486 unsigned Ysub = MovY.getOperand(0).getSubReg(); in matchSwap()
512 I->getOperand(0).getSubReg() != Xsub) { in matchSwap()
DSIFrameLowering.cpp216 Register FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitFlatScratchInit()
217 Register FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitFlatScratchInit()
546 Register RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
547 Register RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
548 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
605 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchSetup()
606 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchSetup()
612 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
641 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
642 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
DSIOptimizeExecMaskingPreRA.cpp216 unsigned CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
220 CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
239 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS); in optimizeVcndVcmpPair()
263 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg()); in optimizeVcndVcmpPair()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp259 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
321 if (!Op.getSubReg()) in profit()
325 if (MI->getOperand(1).getSubReg() != 0) in profit()
444 if (Op.getSubReg()) in isProfitable()
607 unsigned SR = Op.getSubReg(); in createHalfInstr()
653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
678 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
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DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
DHexagonAsmPrinter.cpp136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
540 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
541 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
552 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
553 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
566 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
567 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
DHexagonInstrInfo.cpp127 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
128 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
852 Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
853 Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
1037 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill) in expandPostRAPseudo()
1038 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill); in expandPostRAPseudo()
1045 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1054 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1063 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1078 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
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DHexagonExpandCondsets.cpp179 Sub(Op.getSubReg()) {} in RegisterRef()
324 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
376 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
593 Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
675 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split()
885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
887 PredOp.getSubReg()); in predicateAt()
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DHexagonSplitConst32AndConst64.cpp89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy()
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy()
128 return S.getSubReg(); in run()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp439 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
440 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
441 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
442 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
444 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
445 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
446 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
447 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
449 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
450 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCRegisterInfo.cpp27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo

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