Searched refs:getSubRegClass (Results 1 – 4 of 4) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 178 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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| D | SIInstrInfo.cpp | 5312 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
5319 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
5373 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
5374 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
5439 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
5444 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
5457 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
5546 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
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| D | SIFixSGPRCopies.cpp | 296 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
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| D | SIRegisterInfo.cpp | 1393 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo
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