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Searched refs:gfx10 (Results 1 – 25 of 43) sorted by relevance

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/third_party/mesa3d/src/amd/compiler/
Daco_opcodes.py385 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
386 opcode(name, gfx7, gfx9, gfx10, Format.SOP2, cls)
421 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
422 opcode(name, gfx7, gfx9, gfx10, Format.SOPK, cls)
499 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
500 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
527 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
528 opcode(name, gfx7, gfx9, gfx10, Format.SOPC, InstrClass.Salu)
574 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPP, InstrClass.Salu):
575 opcode(name, gfx7, gfx9, gfx10, Format.SOPP, cls)
[all …]
/third_party/mesa3d/docs/relnotes/
D19.2.0.rst322 - radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the
325 - radeonsi/gfx10: fix tessellation for the legacy pipeline
326 - radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy
328 - radeonsi/gfx10: create the GS copy shader if using legacy streamout
329 - radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
330 - radeonsi/gfx10: fix InstanceID for legacy VS+GS
331 - radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
332 - radeonsi/gfx10: always use the legacy pipeline for streamout
333 - radeonsi/gfx10: finish up Navi14, add PCI ID
334 - radeonsi/gfx10: add AMD_DEBUG=nongg
[all …]
D19.3.0.rst2321 - radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the
2324 - radeonsi/gfx10: fix tessellation for the legacy pipeline
2325 - radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy
2327 - radeonsi/gfx10: create the GS copy shader if using legacy streamout
2328 - radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
2329 - radeonsi/gfx10: fix InstanceID for legacy VS+GS
2330 - radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
2331 - radeonsi/gfx10: always use the legacy pipeline for streamout
2332 - radeonsi/gfx10: finish up Navi14, add PCI ID
2333 - radeonsi/gfx10: add AMD_DEBUG=nongg
[all …]
D20.2.4.rst108 - radeonsi: disable WGP mode on gfx10.3 to prevent hangs
112 - radeonsi/gfx10: flush gfx cs on ngg -> legacy transition
D19.2.1.rst122 - radeonsi/gfx10: fix L2 cache rinse programming
126 - radeonsi/gfx10: fix corruption for chips with harvested TCCs
D21.1.4.rst155 - aco/gfx10: NGG zero output workaround for conservative rasterization.
156 - aco/gfx10: Emit barrier at the start of NGG VS and TES.
D20.0.3.rst158 - radv/gfx10: fix required subgroup size with
160 - radv/gfx10: fix required ballot size with
D20.2.5.rst109 - ac: fix min/max_good_num_cu_per_sa on gfx10.3 with disabled SEs
110 - radeonsi: disable SDMA on gfx6-7 and gfx10.3 to decrease CPU overhead
D20.0.0.rst2289 - radeonsi/gfx10: simplify some duplicated NGG GS code
2290 - radeonsi/gfx10: fix the vertex order for triangle strips emitted by a
2311 - radeonsi/gfx10: disable vertex grouping
2312 - radeonsi/gfx10: simplify the tess_turns_off_ngg condition
2321 - radeonsi/gfx10: don't insert NGG streamout atomics if they are never
2327 - radeonsi/gfx10: fix ngg_get_ordered_id
2330 - radeonsi/gfx10: don't declare any LDS for NGG if it's not used
2331 - radeonsi/gfx10: enable NGG passthrough for eligible shaders
2332 - radeonsi/gfx10: improve performance for TES using PrimID but not
2338 gfx10
[all …]
D19.3.3.rst149 - ac/gpu_info: always use distributed tessellation on gfx10
202 - aco/gfx10: Fix VcmpxExecWARHazard mitigation.
D19.2.7.rst72 - radv/gfx10: fix implementation of exclusive scans
D19.2.5.rst102 - radeonsi: disable sdma for gfx10
D20.1.5.rst114 - radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING
D20.1.6.rst122 - radv/gfx10: add missing initialization of registers
D19.2.3.rst133 - radv/gfx10: fix 3D images
D21.1.3.rst115 - radeonsi: add a gfx10 bug workaround for NOT_EOP
D19.3.2.rst126 - radv/gfx10: fix the out-of-bounds check for vertex descriptors
D20.2.2.rst94 - Revert "radeonsi/gfx10: disable vertex grouping"
D20.0.2.rst34 - [RadeonSI][gfx10/navi] Kerbal Space Program crash: si_draw_vbo:
D22.0.4.rst137 - radeonsi: don't use wave32 for GE on gfx10 if culling is used
D21.1.2.rst133 - radeonsi: add a gfx10 hw bug workaround with the barrier before gs_alloc_req
/third_party/mesa3d/src/amd/addrlib/
Dmeson.build40 'src/gfx10/gfx10addrlib.cpp',
41 'src/gfx10/gfx10addrlib.h',
42 'src/gfx10/gfx10SwizzlePattern.h',
47 'src/chip/gfx10/gfx10_gb_reg.h',
80 'src/chip/gfx10', 'src/chip/gfx11',
/third_party/mesa3d/src/amd/common/
Dmeson.build28 '../registers/gfx10.json',
34 '../registers/gfx10-rsrc.json',
59 '../../util/format/u_format.csv', '../registers/gfx10-rsrc.json', '../registers/gfx11-rsrc.json'
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td416 // gfx10: bits 24-27 indicate the number of active threads/dwords
904 // bit 2 = dlc on gfx10+),
919 // bit 2 = dlc on gfx10+),
934 // bit 2 = dlc on gfx10+),
950 // bit 2 = dlc on gfx10+),
1067 // bit 2 = dlc on gfx10+),
1081 // bit 2 = dlc on gfx10+),
1095 // bit 2 = dlc on gfx10+),
1110 // bit 2 = dlc on gfx10+),
/third_party/mesa3d/docs/
Dfeatures.txt509 VK_KHR_fragment_shading_rate DONE (radv/gfx10.3+)
533 VK_EXT_border_color_swizzle DONE (anv, lvp, tu, radv/gfx10+)
565 VK_EXT_post_depth_coverage DONE (anv/gfx10+, lvp, radv/gfx10+)
605 VK_AMD_shader_fragment_mask DONE (radv/gfx10.3-)

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