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Searched refs:gfx_cs (Results 1 – 25 of 25) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_dma.c161 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), in si_cp_dma_prepare()
164 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), in si_cp_dma_prepare()
171 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_cp_dma_prepare()
276 si_emit_cp_dma(sctx, &sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, cache_policy); in si_cp_dma_realign_engine()
339 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) { in si_cp_dma_copy_buffer()
368 si_emit_cp_dma(sctx, &sctx->gfx_cs, main_dst_offset, main_src_offset, byte_count, dma_flags, in si_cp_dma_copy_buffer()
383 si_emit_cp_dma(sctx, &sctx->gfx_cs, dst_offset, src_offset, skipped_size, dma_flags, in si_cp_dma_copy_buffer()
409 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 0, 4, 0xabcdef01, SI_OP_SYNC_BEFORE_AFTER, in si_test_gds()
411 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 4, 4, 0x23456789, SI_OP_SYNC_BEFORE_AFTER, in si_test_gds()
413 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 8, 4, 0x87654321, SI_OP_SYNC_BEFORE_AFTER, in si_test_gds()
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Dsi_gfx_cs.c36 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_flush_gfx_cs()
114 si_cp_dma_wait_for_idle(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
129 ctx->emit_cache_flush(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
171 si_handle_thread_trace(ctx, &ctx->gfx_cs); in si_flush_gfx_cs()
206 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->current_saved_cs->trace_buf, in si_begin_gfx_cs_debug()
213 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->screen->gds, RADEON_USAGE_READWRITE, 0); in si_add_gds_to_buffer_list()
215 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->screen->gds_oa, RADEON_USAGE_READWRITE, 0); in si_add_gds_to_buffer_list()
337 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) { in si_tmz_preamble()
372 is_secure = ctx->ws->cs_is_secure(&ctx->gfx_cs); in si_begin_new_gfx_cs()
404 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->screen->attribute_ring, in si_begin_new_gfx_cs()
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Dsi_fence.c94 if (!ctx->ws->cs_is_secure(&ctx->gfx_cs)) { in si_cp_release_mem()
116 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, in si_cp_release_mem()
145 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, in si_cp_release_mem()
160 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_WRITE | RADEON_PRIO_QUERY); in si_cp_release_mem()
192 ws->cs_add_fence_dependency(&sctx->gfx_cs, fence, 0); in si_add_fence_dependency()
197 sctx->ws->cs_add_syncobj_signal(&sctx->gfx_cs, fence); in si_add_syncobj_signal()
273 … radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE | RADEON_PRIO_QUERY); in si_fine_fence_set()
274 si_cp_release_mem(ctx, &ctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, in si_fine_fence_set()
484 if (!radeon_emitted(&sctx->gfx_cs, sctx->initial_gfx_cs_size)) { in si_flush_all_queues()
488 ws->cs_sync_flush(&sctx->gfx_cs); in si_flush_all_queues()
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Dsi_state_streamout.c212 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_set_streamout_targets()
217 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_flush_vgt_streamout()
253 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_streamout_begin()
270 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, in si_emit_streamout_begin()
309 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, in si_emit_streamout_begin()
330 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_streamout_end()
344 si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_PS_DONE, 0, EOP_DST_SEL_TC_L2, in si_emit_streamout_end()
364 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, in si_emit_streamout_end()
385 radeon_begin(&sctx->gfx_cs); in si_emit_streamout_enable()
Dsi_compute.c407 if (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics) { in si_emit_initial_compute_regs()
427 (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics)) { in si_emit_initial_compute_regs()
505 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_switch_compute_shader()
551 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->scratch_bo, in si_switch_compute_shader()
562 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo, in si_switch_compute_shader()
602 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in setup_scratch_rsrc_user_sgprs()
645 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_setup_user_sgprs_co_v2()
692 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf, in si_setup_user_sgprs_co_v2()
749 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer, in si_upload_compute_input()
761 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_setup_nir_user_data()
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Dsi_cp_reg_shadowing.c210 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowed_regs->b.b, in si_init_cp_reg_shadowing()
219 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowed_regs, in si_init_cp_reg_shadowing()
222 ac_emulate_clear_state(&sctx->screen->info, &sctx->gfx_cs, si_set_context_reg_array); in si_init_cp_reg_shadowing()
234 sctx->ws->cs_setup_preemption(&sctx->gfx_cs, shadowing_preamble->pm4, in si_init_cp_reg_shadowing()
Dsi_state_viewport.c109 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf, in si_emit_cull_state()
111 radeon_begin(&sctx->gfx_cs); in si_emit_cull_state()
384 radeon_begin(&ctx->gfx_cs); in si_emit_guardband()
401 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_scissors()
497 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_one_viewport()
511 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_viewports()
548 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_emit_depth_ranges()
640 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_window_rectangles()
Dsi_perfcounter.c63 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_instance()
101 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_select()
127 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_start()
129 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address, in si_pc_emit_start()
146 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_stop()
223 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_read()
282 radeon_begin(&sctx->gfx_cs); in si_inhibit_clockgating()
308 si_pc_emit_shaders(&sctx->gfx_cs, query->shaders); in si_pc_query_resume()
310 si_inhibit_clockgating(sctx, &sctx->gfx_cs, true); in si_pc_query_resume()
364 si_inhibit_clockgating(sctx, &sctx->gfx_cs, false); in si_pc_query_suspend()
Dsi_state_draw.cpp104 radeon_begin(&sctx->gfx_cs); in si_emit_spi_map()
440 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_cp_dma_prefetch_inline()
773 uint64_t ring_va = (unlikely(sctx->ws->cs_is_secure(&sctx->gfx_cs)) ? in si_emit_derived_tess_state()
803 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_derived_tess_state()
1152 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_rasterizer_prim_state()
1225 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_vs_state()
1279 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_ia_multi_vgt_param()
1359 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in gfx10_emit_ge_cntl()
1376 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_draw_registers()
1424 radeon_begin(&sctx->gfx_cs); \
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Dsi_pm4.c139 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pm4_emit()
142 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo, in si_pm4_emit()
Dsi_test_dma_perf.c175 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_test_dma_perf()
188 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, 0, size, clear_value, in si_test_dma_perf()
239 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_test_dma_perf()
Dsi_buffer.c36 return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage); in si_cs_is_buffer_referenced()
42 return sctx->ws->buffer_map(sctx->ws, resource->buf, &sctx->gfx_cs, usage); in si_buffer_map()
744 if (radeon_emitted(&ctx->gfx_cs, ctx->initial_gfx_cs_size) && in si_resource_commit()
745 ctx->ws->cs_is_buffer_referenced(&ctx->gfx_cs, res->buf, RADEON_USAGE_READWRITE)) { in si_resource_commit()
748 ctx->ws->cs_sync_flush(&ctx->gfx_cs); in si_resource_commit()
Dsi_debug.c391 si_parse_current_ib(f, &sctx->gfx_cs, 0, sctx->gfx_cs.prev_dw + sctx->gfx_cs.current.cdw, in si_print_current_ib()
422 si_parse_current_ib(f, &ctx->gfx_cs, chunk->gfx_begin, chunk->gfx_end, &last_trace_id, in si_log_chunk_type_cs_print()
445 unsigned gfx_cur = ctx->gfx_cs.prev_dw + ctx->gfx_cs.current.cdw; in si_log_cs()
Dsi_state_shaders.cpp772 radeon_begin(&sctx->gfx_cs); in si_emit_shader_es()
933 radeon_begin(&sctx->gfx_cs); in si_emit_shader_gs()
988 ac_set_reg_cu_en(&sctx->gfx_cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, in si_emit_shader_gs()
996 ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, in si_emit_shader_gs()
1004 radeon_begin_again(&sctx->gfx_cs); in si_emit_shader_gs()
1187 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tail()
1217 radeon_begin_again(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tail()
1222 ac_set_reg_cu_en(&sctx->gfx_cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, in gfx10_emit_shader_ngg_tail()
1227 ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, in gfx10_emit_shader_ngg_tail()
1260 radeon_begin(&sctx->gfx_cs); in gfx10_emit_shader_ngg_tess_nogs()
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Dsi_state_binning.c407 radeon_begin(&sctx->gfx_cs); in si_emit_dpbb_disable()
509 radeon_begin(&sctx->gfx_cs); in si_emit_dpbb_state()
Dsi_pipe.c314 sctx->ws->cs_destroy(&sctx->gfx_cs); in si_destroy_context()
406 si_write_user_event(sctx, &sctx->gfx_cs, UserEventTrigger, string, len); in si_emit_string_marker()
531 ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->has_graphics ? AMD_IP_GFX : AMD_IP_COMPUTE, in si_create_context()
745 assert(sctx->gfx_cs.current.cdw == 0); in si_create_context()
769 assert(sctx->gfx_cs.current.cdw == sctx->initial_gfx_cs_size); in si_create_context()
829 sctx->initial_gfx_cs_size = sctx->gfx_cs.current.cdw; in si_create_context()
Dsi_descriptors.c166 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, in si_upload_descriptors()
185 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, desc->buffer, in si_add_descriptors_to_bo_list()
1003 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, in si_update_ps_colorbuf0_slot()
1121 sctx, &sctx->gfx_cs, si_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs()
1178 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, in si_vertex_buffers_begin_new_cs()
1185 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->vb_descriptors_buffer, in si_vertex_buffers_begin_new_cs()
1569 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), in si_set_ring_buffer()
1917 sctx->emit_cache_flush(sctx, &sctx->gfx_cs); in si_upload_bindless_descriptors()
2176 radeon_begin(&sctx->gfx_cs); in si_emit_global_shader_pointers()
2224 radeon_begin(&sctx->gfx_cs); in si_emit_graphics_shader_pointers()
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Dsi_query.c809 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_query_hw_do_emit_start()
895 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, in si_query_hw_do_emit_start()
929 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_query_hw_do_emit_stop()
998 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf, in si_query_hw_do_emit_stop()
1040 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in emit_set_predicate()
1056 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_READ | RADEON_PRIO_QUERY); in emit_set_predicate()
1655 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x80000000, 0x80000000, WAIT_REG_MEM_EQUAL); in si_query_hw_get_result_resource()
Dgfx10_query.c179 si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, in gfx10_sh_query_end()
403 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x00000001, 0x00000001, 0); in gfx10_sh_query_get_result_resource()
Dsi_pipe.h945 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */ member
1944 struct radeon_cmdbuf *cs = &ctx->gfx_cs; in si_need_gfx_cs_space()
1953 if (radeon_cs_memory_below_limit(ctx->screen, &ctx->gfx_cs, kb) && in si_need_gfx_cs_space()
1999 …!radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usag… in radeon_add_to_gfx_buffer_list_check_mem()
2002 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage); in radeon_add_to_gfx_buffer_list_check_mem()
Dsi_state.c73 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_cb_render_state()
806 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_blend_color()
840 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_clip_state()
874 radeon_begin(&sctx->gfx_cs); in si_emit_clip_regs()
1237 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_stencil_ref()
1571 radeon_begin(&sctx->gfx_cs); in si_emit_db_render_state()
3202 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_emit_framebuffer_state()
3230 … sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC | in si_emit_framebuffer_state()
3234 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer, in si_emit_framebuffer_state()
3469 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | in si_emit_framebuffer_state()
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Dsi_sqtt.c1105 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_sqtt_describe_pipeline_bind()
Dsi_compute_blit.c465 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, offset, aligned_size, *clear_value, in si_clear_buffer()
/third_party/mesa3d/docs/relnotes/
D21.0.0.rst2199 - radeonsi: initialize ctx and gfx_cs first, then allocators
D21.3.0.rst2613 - radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers