Searched refs:gs_vtx_offset (Results 1 – 8 of 8) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_shader_args.c | 755 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]); in radv_declare_shader_args()
756 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[1]); in radv_declare_shader_args()
759 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]); in radv_declare_shader_args()
784 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]); in radv_declare_shader_args()
785 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[1]); in radv_declare_shader_args()
787 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]); in radv_declare_shader_args()
788 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[3]); in radv_declare_shader_args()
789 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[4]); in radv_declare_shader_args()
790 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[5]); in radv_declare_shader_args()
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| D | radv_nir_lower_abi.c | 114 … return ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_vtx_offset[nir_intrinsic_base(intrin)]); in lower_abi_instr()
126 return ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_vtx_offset[0]); in lower_abi_instr()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_shader_args.h | 115 struct ac_arg gs_vtx_offset[6]; /* GFX6-8: [0-5], GFX9+: [0-2] packed */ member
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_llvm_gs.c | 77 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[0], vgpr++); in si_set_es_return_value_for_gs()
78 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[1], vgpr++); in si_set_es_return_value_for_gs()
81 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[2], vgpr++); in si_set_es_return_value_for_gs()
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| D | si_shader.c | 603 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[0]); in si_init_shader_args()
604 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[1]); in si_init_shader_args()
607 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[2]); in si_init_shader_args()
676 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[0]); in si_init_shader_args()
677 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[1]); in si_init_shader_args()
679 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[2]); in si_init_shader_args()
680 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[3]); in si_init_shader_args()
681 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[4]); in si_init_shader_args()
682 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[5]); in si_init_shader_args()
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| D | gfx10_shader_ngg.c | 160 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args.gs_vtx_offset[0]); in gfx10_ngg_build_export_prim()
204 prim.index[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); in gfx10_ngg_build_export_prim()
1147 vtxindex[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); in gfx10_ngg_culling_build_end()
1574 vtxindex[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[0], 10 * i, 9); in gfx10_ngg_build_end()
1577 vtxindex[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); in gfx10_ngg_build_end()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.3.0.rst | 4132 - radv, ac, aco: Use indices 0-2 of gs_vtx_offset argument array on GFX9+.
4133 - radeonsi: Change GS vertex offset arguments to use gs_vtx_offset array.
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| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_nir_to_llvm.c | 4048 result = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[nir_intrinsic_base(instr)]); in visit_intrinsic()
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