Searched refs:hasVGPRs (Results 1 – 6 of 6) sorted by relevance
130 return !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()149 return hasAGPRs(RC) && !hasVGPRs(RC); in isAGPRClass()153 bool hasVGPRs(const TargetRegisterClass *RC) const;160 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
286 if (TRI->hasVGPRs(RC)) { in getPhysRegBank()313 if (TRI->hasVGPRs(RC)) { in getRegBankMask()443 if (TRI->hasVGPRs(RC)) in isReassignable()
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg))) in findSRegBaseAndIndex()
1273 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo1691 return hasVGPRs(RC); in isVGPR()
705 Opcode = RI.hasVGPRs(RI.getPhysRegClass(SrcReg)) ? in copyPhysReg()707 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(RI.getPhysRegClass(SrcReg))) { in copyPhysReg()2142 return RI.hasVGPRs(RC) && NumInsts <= 6; in canInsertSelect()3327 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()4607 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()5776 if (RI.hasVGPRs(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
1186 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass))) in legalizeScalarOperands()