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Searched refs:inline_push_constant_mask (Results 1 – 7 of 7) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_shader_args.c73 uint64_t inline_push_constant_mask; member
126 if (!info->inline_push_constant_mask) in allocate_inline_push_consts()
129 uint64_t mask = info->inline_push_constant_mask; in allocate_inline_push_consts()
148 user_sgpr_info->inline_push_constant_mask = mask; in allocate_inline_push_consts()
268 for (unsigned i = 0; i < util_bitcount64(user_sgpr_info->inline_push_constant_mask); i++) { in declare_global_input_sgprs()
271 args->ac.inline_push_const_mask = user_sgpr_info->inline_push_constant_mask; in declare_global_input_sgprs()
494 if (user_sgpr_info->inline_push_constant_mask) { in set_global_input_locs()
496 util_bitcount64(user_sgpr_info->inline_push_constant_mask)); in set_global_input_locs()
Dradv_shader.h242 uint64_t inline_push_constant_mask; member
Dradv_device_generated_commands.c1265 … desc[idx * 3 + 1] = graphics_pipeline->base.shaders[i]->info.inline_push_constant_mask; in radv_prepare_dgc()
1266 … desc[idx * 3 + 2] = graphics_pipeline->base.shaders[i]->info.inline_push_constant_mask >> 32; in radv_prepare_dgc()
Dradv_shader_info.c99 info->inline_push_constant_mask |= u_bit_consecutive64(start, size); in gather_push_constant_info()
Dradv_pipeline.c3723 stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask = in radv_declare_pipeline_args()
3738 stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask = in radv_declare_pipeline_args()
3750 stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask; in radv_declare_pipeline_args()
4500 info.inline_push_constant_mask = gs_copy_args.ac.inline_push_const_mask; in radv_pipeline_create_gs_copy_shader()
Dradv_shader.c2454 info.inline_push_constant_mask = args.ac.inline_push_const_mask;
Dradv_cmd_buffer.c3557 const uint64_t mask = shader->info.inline_push_constant_mask; in radv_emit_all_inline_push_consts()