| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 606 bool isAdd = true; in EncodeAddrModeOpValues() local
611 isAdd = false; in EncodeAddrModeOpValues()
617 isAdd = false; in EncodeAddrModeOpValues()
621 return isAdd; in EncodeAddrModeOpValues()
987 bool isAdd = true; in getAddrModeImm12OpValue() local
996 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
1011 isAdd = false; in getAddrModeImm12OpValue()
1014 isAdd = false; in getAddrModeImm12OpValue()
1019 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
1023 if (isAdd) in getAddrModeImm12OpValue()
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| D | ARMAsmBackend.cpp | 485 bool isAdd = true; in adjustFixupValue() local
488 isAdd = false; in adjustFixupValue()
494 Value |= isAdd << 23; in adjustFixupValue()
714 bool isAdd = true; in adjustFixupValue() local
717 isAdd = false; in adjustFixupValue()
725 return Value | (isAdd << 23); in adjustFixupValue()
734 bool isAdd = true; in adjustFixupValue() local
737 isAdd = false; in adjustFixupValue()
745 Value |= isAdd << 23; in adjustFixupValue()
761 bool isAdd = true; in adjustFixupValue() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 277 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 795 bool isAdd; member
2874 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
3095 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3097 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3106 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3109 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3116 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3124 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
3648 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2736 // {12} isAdd
2754 // {12} isAdd
2846 // {12} isAdd
2865 // {12} isAdd
2882 // {12} isAdd
2901 // {12} isAdd
3007 // {12} isAdd
3025 // {12} isAdd
3169 // {12} isAdd
3188 // {12} isAdd
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| D | ARMInstrFormats.td | 791 // {12} isAdd
809 // {12} isAdd
830 // {12} isAdd
883 // {8} isAdd
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| D | ARMBaseInstrInfo.cpp | 600 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add; in isLdstScaledRegNotPlusLsl2() local
604 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2); in isLdstScaledRegNotPlusLsl2()
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| D | ARMInstrThumb.td | 945 let isAdd = 1 in {
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| D | ARMInstrThumb2.td | 2269 let isAdd = 1 in
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 442 if (DI->getDesc().isAdd()) { in findInductionRegister()
1641 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
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| D | HexagonDepInstrInfo.td | 221 let isAdd = 1;
237 let isAdd = 1;
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8664.cpp | 4444 static bool isAdd(const Inst *Instr) { in isAdd() function in Ice::X8664::AddressOptimizer
4539 if (isAdd(BaseInst) && in matchCombinedBaseIndex()
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| D | IceTargetLoweringX8632.cpp | 5023 static bool isAdd(const Inst *Instr) { in isAdd() function in Ice::X8632::AddressOptimizer
5118 if (isAdd(BaseInst) && in matchCombinedBaseIndex()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 512 bit isAdd = 0; // Is this instruction an add instruction?
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 39024 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
39029 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
39034 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
39039 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
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