| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 289 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
443 assert(!(DependenceMO.isDef() && in canHoistInst()
602 return MO.isReg() && MO.getReg() && MO.isDef() && in analyzeBlockForNullChecks()
649 assert(MO.isDef() && "Expected def or use"); in insertFaultingInstr()
691 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
701 if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead()) in rewriteNullChecks()
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| D | LiveRangeCalc.cpp | 83 if (!MO.isDef() && !MO.readsReg()) in calculate()
99 if (MO.isDef()) in calculate()
107 if (MO.isDef() && !LI.hasSubRanges()) in calculate()
174 if (!MO.readsReg() || (IsSubRange && MO.isDef())) in extendToUses()
180 if (MO.isDef()) in extendToUses()
192 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses()
200 if (MO.isDef()) in extendToUses()
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| D | MachineOperand.cpp | 92 if (isDef()) in substPhysReg()
127 if (isDef()) in isRenamable()
234 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, in ChangeToRegister() argument
247 assert(!(isDead && !isDef) && "Dead flag on non-def"); in ChangeToRegister()
248 assert(!(isKill && isDef) && "Kill flag on def"); in ChangeToRegister()
252 IsDef = isDef; in ChangeToRegister()
282 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo()
348 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
733 OS << (isDef() ? "implicit-def " : "implicit "); in print()
734 else if (PrintDef && isDef()) in print()
[all …]
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| D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) in findComponents()
190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents()
219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands()
224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands()
346 if (!MO.isDef()) in computeMainRangesFixFlags()
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| D | LiveRangeEdit.cpp | 192 if (MO.isDef()) { in foldAsLoad()
292 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef()
316 else if (MOI->isDef()) in eliminateDeadDef()
326 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) || in eliminateDeadDef()
331 if (MOI->isDef()) { in eliminateDeadDef()
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| D | MachineInstrBundle.cpp | 153 if (MO.isDef()) { in finalizeBundle()
297 if (MO.isDef()) in AnalyzeVirtRegInBundle()
302 if (MO.isDef()) in AnalyzeVirtRegInBundle()
344 } else if (MO.isDef()) { in AnalyzePhysRegInBundle()
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| D | MIRCanonicalizerPass.cpp | 173 if (!MO.isDef()) in rescheduleCanonically()
189 if (!MO.isDef()) in rescheduleCanonically()
357 if (!MO.isDef() && MO.isKill()) { in doDefKillClear()
362 if (MO.isDef() && MO.isDead()) { in doDefKillClear()
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| D | RegisterScavenging.cpp | 148 assert(MO.isDef()); in determineKillsAndDefs()
244 assert(MO.isDef()); in forward()
334 if (MO.isDef()) in findSurvivorReg()
637 if (MO.isDef()) { in scavengeVReg()
729 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
733 if (MO.isDef()) { in scavengeFrameVirtualRegsInBlock()
744 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
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| D | MachineLICM.cpp | 468 if (!MO.isDef()) { in ProcessMI()
590 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
615 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
805 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
900 if (MO.isDef()) in calcRegisterCost()
1097 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse()
1167 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1266 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist()
1420 if (MO.isReg() && MO.isDef() && in EliminateCSE()
1531 if (MO.isReg() && MO.isDef() && !MO.isDead()) in Hoist()
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| D | LiveRegUnits.cpp | 52 if (MOP.isDef()) in stepBackward()
71 if (!MOP.isDef() && !MOP.readsReg()) in accumulate()
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| D | CriticalAntiDepBreaker.cpp | 287 if (!MO.isDef()) continue; in ScanInstruction()
366 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs()
377 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs()
383 if (RefOper->isDef()) in isNewRegClobberedByRefs()
632 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
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| D | VirtRegMap.cpp | 530 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || in rewrite()
531 (MO.isDef() && subRegLiveThrough(*MI, PhysReg))) in rewrite()
534 if (MO.isDef()) { in rewrite()
549 assert(MO.isDef()); in rewrite()
557 if (MO.isDef()) { in rewrite()
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| D | LivePhysRegs.cpp | 52 if (MOP.isDef()) in removeDefs()
88 if (O->isDef()) { in stepForward()
288 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
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| D | MachineInstr.cpp | 626 if (MO.isDef()) { in isIdenticalTo()
684 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
725 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs()
1001 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
1053 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1412 if (!Operand.isReg() || Operand.isDef()) in hasComplexRegisterTies()
1491 if (MO.isReg() && MO.isTied() && !MO.isDef()) in print()
1501 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in print()
1874 if (!MO.isReg() || !MO.isDef()) in addRegisterDead()
1919 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) in clearRegisterDeads()
[all …]
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| D | DeadMachineInstructionElim.cpp | 78 if (MO.isReg() && MO.isDef()) { in isDead()
152 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
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| D | MachineCSE.cpp | 284 if (!MO.isReg() || MO.isDef()) in hasLivePhysRegDefUses()
303 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses()
380 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach()
597 if (!MO.isReg() || !MO.isDef()) in ProcessBlockCSE()
826 assert(MI->getOperand(0).isDef() && in ProcessBlockPRE()
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| D | AggressiveAntiDepBreaker.cpp | 240 if (MO.isDef()) in IsImplicitDefUse()
253 if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) || in GetPassthruRegs()
367 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
377 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
420 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
720 if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber()) in FindSuitableFreeRegisters()
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| D | RegAllocFast.cpp | 879 if (MO.isDef() && MO.isUndef()) in setPhysReg()
907 if (!MO.isReg() || !MO.isDef()) continue; in handleThroughOperands()
963 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; in handleThroughOperands()
1146 if (!MO.isDef() && !MO.isTied()) continue; in allocateInstruction()
1168 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) in allocateInstruction()
1181 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) in allocateInstruction()
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| D | MachineCopyPropagation.cpp | 479 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() || in forwardUses()
621 if (!MO.isReg() || !MO.isDef()) in ForwardCopyPropagateBlock()
663 if (MO.isDef() && !MO.isEarlyClobber()) { in ForwardCopyPropagateBlock()
846 if (MO.isDef()) in BackwardCopyPropagateBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 154 if (MO.isDef()) in repairReg()
175 if (MO.isDef()) { in repairReg()
247 assert(CurRegBank || MO.isDef()); in getRepairCost()
266 if (MO.isDef()) in getRepairCost()
339 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?"); in tryAvoidingSplit()
342 if (!MO.isDef()) { in tryAvoidingSplit()
366 assert(MI.isTerminator() && MO.isDef() && in tryAvoidingSplit()
736 bool Before = !MO.isDef(); in RepairingPlacement()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 373 bool isDef() const { in isDef() function
753 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
779 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
786 assert(!(isDead && !isDef) && "Dead flag on non-def");
787 assert(!(isKill && isDef) && "Kill flag on def");
789 Op.IsDef = isDef;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 374 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
501 if (Op.isDef()) { in updateDeadsInRange()
674 assert(MD.isDef()); in split()
730 if (!Op.isReg() || !Op.isDef()) in isPredicable()
766 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
812 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) in canMoveOver()
879 if (!MO.isReg() || !MO.isDef()) in predicateAt()
927 assert(!Op.isDef() && "Not expecting a def"); in renameInRange()
1006 ReferenceMap &Map = Op.isDef() ? Defs : Uses; in predicate()
1007 if (Op.isDef() && Op.isUndef()) { in predicate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 264 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead()
266 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg())) in getSuperRegDestIfDead()
340 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFormMemoryClauses.cpp | 126 if (!MO.isReg() || MO.isDef()) in isValidClauseInst()
226 RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
276 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 210 if (MO.isDef()) { in delayHasHazard()
239 if (MO.isDef()) in insertDefsUses()
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