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Searched refs:isReg (Results 1 – 25 of 335) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsInstPrinter.cpp31 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
241 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineOperand.h220 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
223 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
228 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
319 bool isReg() const { return OpKind == MO_Register; } in isReg() function
359 assert(isReg() && "This is not a register operand!"); in getReg()
364 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
369 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
374 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
379 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
384 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
85 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
97 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
110 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
128 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
146 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
168 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
183 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp112 if (MCOp.isReg()) in getMachineOpValue()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
150 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineInstr.cpp163 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
172 if (MO.isReg()) in AddRegOperandsToUseLists()
219 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
267 if (NewMO->isReg()) { in addOperand()
302 if (Operands[i].isReg()) in RemoveOperand()
307 if (MRI && Operands[OpNo].isReg()) in RemoveOperand()
617 if (!MO.isReg()) { in isIdenticalTo()
684 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
711 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
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DImplicitNullChecks.cpp279 if (!(MOA.isReg() && MOA.getReg())) in canReorder()
284 if (!(MOB.isReg() && MOB.getReg())) in canReorder()
370 !BaseOp->isReg() || BaseOp->getReg() != PointerReg) in isSuitableMemoryOp()
417 if (!(DependenceMO.isReg() && DependenceMO.getReg())) in canHoistInst()
478 if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 && in analyzeBlockForNullChecks()
602 return MO.isReg() && MO.getReg() && MO.isDef() && in analyzeBlockForNullChecks()
644 if (MO.isReg()) { in insertFaultingInstr()
691 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
701 if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead()) in rewriteNullChecks()
DMachineSink.cpp435 if (MO.isReg() && MO.getReg().isVirtual()) in ProcessDbgInst()
465 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
664 if (!MO.isReg()) continue; // Ignore non-register operands. in FindSuccToSinkTo()
770 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
780 return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 && in SinkingPreventsImplicitNullCheck()
915 if (!MO.isReg()) continue; in SinkInstruction()
988 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) in SinkInstruction()
1022 if (MO.isReg() && MO.isUse()) in SinkInstruction()
1032 assert(MI.getOperand(1).isReg()); in SalvageUnsunkDebugUsersOfCopy()
1040 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) in SalvageUnsunkDebugUsersOfCopy()
[all …]
DMIRCanonicalizerPass.cpp167 if (!MO.isReg()) in rescheduleCanonically()
187 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) in rescheduleCanonically()
199 if (II->getOperand(i).isReg()) { in rescheduleCanonically()
315 if (!MI->getOperand(0).isReg()) in propagateLocalCopies()
317 if (!MI->getOperand(1).isReg()) in propagateLocalCopies()
355 if (!MO.isReg()) in doDefKillClear()
DMachineLICM.cpp460 if (!MO.isReg()) in ProcessMI()
562 if (!MO.isReg()) in HoistRegionPostRA()
590 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
615 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
805 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
888 if (!MO.isReg() || MO.isImplicit()) in calcRegisterCost()
959 if (MO.isReg()) { in isInvariantStore()
1045 if (!MO.isReg()) in IsLoopInvariantInst()
1097 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse()
1140 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIOptimizeExecMasking.cpp68 if (Src.isReg() && in isCopyFromExec()
84 if (Dst.isReg() && in isCopyToExec()
86 MI.getOperand(1).isReg()) in isCopyToExec()
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
130 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
394 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in runOnMachineFunction()
396 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in runOnMachineFunction()
DSIFoldOperands.cpp53 assert(FoldOp->isReg() || FoldOp->isGlobal()); in FoldCandidate()
66 bool isReg() const { in isReg() function
190 assert(Old.isReg()); in updateOperand()
390 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
391 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
409 if (!OtherOp.isReg() || in tryAddToFoldList()
480 assert (Sub->isReg()); in getRegSeqInit()
483 SubDef && Sub->isReg() && !Sub->getSubReg() && in getRegSeqInit()
492 if (!Op->isReg()) in getRegSeqInit()
524 if (!OpToFold.isReg()) in tryToFoldACImm()
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DSIOptimizeExecMaskingPreRA.cpp113 if (Op->isReg() && Op->getReg() != Exec) in getOrNonExecReg()
116 if (Op->isReg() && Op->getReg() != Exec) in getOrNonExecReg()
211 !And->getOperand(1).isReg() || !And->getOperand(2).isReg()) in optimizeVcndVcmpPair()
233 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
235 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
250 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
358 if (Op.isReg()) in runOnMachineFunction()
399 if (Op.isReg()) in runOnMachineFunction()
DSIPeepholeSDWA.cpp115 assert(Target->isReg()); in SDWAOperand()
116 assert(Replaced->isReg()); in SDWAOperand()
272 assert(To.isReg() && From.isReg()); in copyRegOperand()
284 return LHS.isReg() && in isSameReg()
285 RHS.isReg() && in isSameReg()
292 if (!Reg->isReg() || !Reg->isDef()) in findSingleRegUse()
314 if (!Reg->isReg()) in findSingleRegDef()
322 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
373 assert(Src && (Src->isReg() || Src->isImm())); in convertToSDWA()
415 assert(Src && Src->isReg()); in convertToSDWA()
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DSIShrinkInstructions.cpp79 if (Src0.isReg()) { in foldImmediates()
177 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyExtraImplicitOps()
185 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare()
280 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() && in shrinkMIMG()
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) { in shrinkScalarLogicOp()
369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
393 if (!MO.isReg()) in instAccessReg()
464 if (!Xop.isReg()) in matchSwap()
638 if (!Src0->isReg() && Src1->isReg()) { in runOnMachineFunction()
646 if (Register::isVirtualRegister(Dest->getReg()) && Src0->isReg()) { in runOnMachineFunction()
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DSIInstrInfo.cpp278 if (!BaseOp || !BaseOp->isReg()) in getMemOperandWithOffset()
314 if (!BaseOp->isReg()) in getMemOperandWithOffset()
327 if (SOffset && SOffset->isReg()) { in getMemOperandWithOffset()
358 if (!BaseOp->isReg()) in getMemOperandWithOffset()
373 if (!BaseOp->isReg()) in getMemOperandWithOffset()
393 if (!BaseOp->isReg()) in getMemOperandWithOffset()
407 if (!BaseOp1.isReg() || !BaseOp2.isReg()) in memOpsHaveSameBasePtr()
630 assert(DefOp.isReg() || DefOp.isImm()); in copyPhysReg()
632 if (DefOp.isReg()) { in copyPhysReg()
1444 assert(SrcOp.isReg()); in expandPostRAPseudo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp321 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg || in updateKillFlags()
374 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
499 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
582 if (SO.isReg()) { in getCondTfrOpcode()
642 if (SrcOp.isReg()) { in genCondTfrFor()
681 if (Op.isReg()) in split()
690 if (ST.isReg() && SF.isReg()) { in split()
730 if (!Op.isReg() || !Op.isDef()) in isPredicable()
766 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
800 if (!Op.isReg()) in canMoveOver()
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DHexagonVLIWPacketizer.cpp151 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
313 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit()) in isCallDependent()
388 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
430 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
578 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
582 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
588 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
594 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
652 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
705 if (!MO.isReg()) in canPromoteToNewValueStore()
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DHexagonHardwareLoops.cpp341 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anon423929db0111::CountValue
345 assert(isReg() && "Wrong CountValue accessor"); in getReg()
350 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
360 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
677 if (Op1.isReg()) { in getLoopTripCount()
697 if (InitialValue->isReg()) { in getLoopTripCount()
707 if (EndValue->isReg()) { in getLoopTripCount()
737 if (Start->isReg()) { in computeCount()
743 if (End->isReg()) { in computeCount()
750 if (!Start->isReg() && !Start->isImm()) in computeCount()
[all …]
DHexagonNewValueJump.cpp152 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY()
177 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
566 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction()
573 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction()
602 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
653 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
706 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
709 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
DHexagonSplitDouble.cpp179 if (MI->getOperand(1).isReg()) in isFixedInstr()
184 if (MI->getOperand(0).isReg()) in isFixedInstr()
211 if (!Op.isReg()) in isFixedInstr()
259 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
443 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
500 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch"); in collectIndRegsForLoop()
601 if (!Op.isReg()) { in createHalfInstr()
704 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
732 assert(Op0.isReg()); in splitCombine()
740 if (!Op1.isReg()) { in splitCombine()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiDelaySlotFiller.cpp108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
110 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
115 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
117 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
207 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
236 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
DLanaiMemAluCombiner.cpp185 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
264 if (AluOffset.isReg()) in insertMergedInstruction()
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr()
356 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCCodeEmitter.cpp127 if (MO.isReg()) in getMachineOpValue()
154 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
189 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
202 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
215 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
DAVRMCCodeEmitter.cpp71 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && in loadStorePostEncoder()
119 assert(MO.isReg()); in encodeLDSTPtrReg()
140 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
254 if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXProxyRegErasure.cpp99 assert(InOp.isReg() && "ProxyReg input operand should be a register."); in replaceMachineInstructionUsage()
100 assert(OutOp.isReg() && "ProxyReg output operand should be a register."); in replaceMachineInstructionUsage()
113 if (Op.isReg() && Op.getReg() == From.getReg()) { in replaceRegisterUsage()

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