Searched refs:isSGPRClass (Results 1 – 11 of 11) sorted by relevance
129 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass() function135 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()144 return isSGPRClass(RC); in isSGPRReg()217 return !isSGPRClass(RC); in isDivergentRegClass()
191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()198 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()247 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()293 assert(TRI->isSGPRClass(SrcRC) && in foldVGPRCopyIntoRegSequence()680 if (TRI->isSGPRClass(DstRC) && in runOnMachineFunction()796 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()819 if (TRI->isSGPRClass(RC)) in processPHINode()
690 if (RI.isSGPRClass(RC)) { in copyPhysReg()700 if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) { in copyPhysReg()794 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()978 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()979 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()981 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()1070 if (RI.isSGPRClass(RC)) { in storeRegToStackSlot()1199 if (RI.isSGPRClass(RC)) { in loadRegFromStackSlot()2159 return RI.isSGPRClass(RC); in canInsertSelect()2383 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()[all …]
90 return STI->isSGPRClass(RC) ? in getRegKind()
970 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()1055 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) in fixVcmpxExecWARHazard()
124 unsigned AndOpc = TRI.isSGPRClass(SrcRC) ? in selectCOPY()1439 IsSgpr = TRI.isSGPRClass(RC); in selectG_CONSTANT()
648 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) { in foldOperand()
1400 if (isSGPRClass(RC)) { in getSubRegClass()
2660 if (!RC || SIRI->isSGPRClass(RC)) in isVGPRImm()
3353 if (!TII->getRegisterInfo().isSGPRClass(IdxRC)) in setM0ToIndexFromSGPR()10999 if (!TRI->isSGPRClass(RC) && !isDivergent) in getRegClassFor()11001 else if (TRI->isSGPRClass(RC) && isDivergent) in getRegClassFor()11090 else if (SIRI->isSGPRClass(RC)) in requiresUniformRegister()
224 if (TRI->isSGPRClass(&RC)) { in getRegBankFromRegClass()