Searched refs:isSGPRReg (Results 1 – 12 of 12) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 708 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && in runOnMachineFunction()
710 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && in runOnMachineFunction()
777 !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) { in processPHINode()
788 if (!TRI->isSGPRReg(*MRI, Use.getReg()) && in processPHINode()
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| D | SIFixupVectorISel.cpp | 141 if (!TRI->isSGPRReg(MRI, BaseReg)) in findSRegBaseAndIndex()
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| D | SIRegisterInfo.h | 138 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const { in isSGPRReg() function
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| D | SIFoldOperands.cpp | 753 if (TRI->isSGPRReg(*MRI, Src.Reg)) { in foldOperand()
822 if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) { in foldOperand()
1032 bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg()); in tryConstantFoldOp()
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| D | SILowerI1Copies.cpp | 105 return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) && in isLaneMaskReg()
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| D | SIWholeQuadMode.cpp | 547 if (TRI->isSGPRReg(*MRI, Op.getReg())) { in requiresCorrectState()
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| D | SIInstrInfo.h | 677 return !RI.isSGPRReg(MRI, Dest); in isVGPRCopy()
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| D | GCNHazardRecognizer.cpp | 792 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg())) in checkRWLaneHazards()
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| D | SIPeepholeSDWA.cpp | 1190 TRI->isSGPRReg(*MRI, Op.getReg())) { in legalizeScalarOperands()
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| D | SIInstrInfo.cpp | 2666 !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) { in convertToThreeAddress()
2801 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg())) in mayReadEXEC()
4036 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) || in legalizeOperandsVOP2()
5505 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) { in splitScalar64BitXnor()
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| D | SIInsertWaitcnts.cpp | 486 } else if (TRI->isSGPRReg(MRIA, Op.getReg())) { in getRegInterval()
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| D | SIISelLowering.cpp | 10464 !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg())) in AdjustInstrPostInstrSelection()
10888 return !TRI.isSGPRReg(MRI, Reg); in isSDNodeSourceOfDivergence()
10893 if (!TRI.isSGPRReg(MRI, Reg)) in isSDNodeSourceOfDivergence()
10905 return !TRI.isSGPRReg(MRI, Reg); in isSDNodeSourceOfDivergence()
11088 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg)) in requiresUniformRegister()
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