Searched refs:isVGPR (Results 1 – 12 of 12) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 209 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
212 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
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| D | GCNHazardRecognizer.cpp | 592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
727 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
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| D | SIInsertWaitcnts.cpp | 482 if (TRI->isVGPR(MRIA, Op.getReg())) { in getRegInterval()
513 assert(TRI->isVGPR(*MRI, Opnd.getReg())); in setExpScore()
577 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) { in updateByEvent()
625 TRI->isVGPR(MRIA, DefMO.getReg())) { in updateByEvent()
633 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) { in updateByEvent()
1001 if (TRI->isVGPR(MRIA, Op.getReg())) { in generateWaitcntInstBefore()
1044 if (TRI->isVGPR(MRIA, Def.getReg())) { in generateWaitcntInstBefore()
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| D | SIPreAllocateWWMRegs.cpp | 96 if (!TRI->isVGPR(*MRI, Reg)) in processDef()
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| D | SIShrinkInstructions.cpp | 472 if (!TRI.isVGPR(MRI, X)) in matchSwap()
488 if (!TRI.isVGPR(MRI, Y) || MovT.getParent() != MovY.getParent()) in matchSwap()
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| D | SIFoldOperands.cpp | 410 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg())) in tryAddToFoldList()
786 TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg())) in foldOperand()
788 else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) && in foldOperand()
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| D | SIInsertSkips.cpp | 253 if (TRI->isVGPR(MBB.getParent()->getRegInfo(), in kill()
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| D | SIRegisterInfo.cpp | 565 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32 in spillVGPRtoAGPR()
1687 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, in isVGPR() function in SIRegisterInfo
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| D | SIWholeQuadMode.cpp | 861 if (TRI->isVGPR(*MRI, Reg)) { in lowerCopyInstrs()
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| D | SIInstrInfo.cpp | 2342 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg()); in FoldImmediate()
3015 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
3024 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
3035 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
4045 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
4051 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
4077 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
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| D | SIInstrInfo.h | 685 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());}); in hasVGPRUses()
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| D | SIPeepholeSDWA.cpp | 1181 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) in legalizeScalarOperands()
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