Searched refs:is_3src (Results 1 – 11 of 11) sorted by relevance
| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_isa_info.h | 77 is_3src(const struct brw_isa_info *isa, enum opcode opcode) in is_3src() function
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| D | test_eu_compact.cpp | 105 is_3src(isa, brw_inst_opcode(isa, inst))) { in clear_pad_bits()
125 if (is_3src(isa, brw_inst_opcode(isa, src))) { in skip_bit()
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| D | brw_ir.h | 93 bool is_3src(const struct brw_compiler *compiler) const;
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| D | brw_fs_bank_conflicts.cpp | 648 } else if (inst->is_3src(v->compiler) && in shader_conflict_weight_matrix()
947 return is_3src(isa, inst->opcode) && in has_bank_conflict()
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| D | brw_shader.cpp | 885 backend_instruction::is_3src(const struct brw_compiler *compiler) const in is_3src() function in backend_instruction
887 return ::is_3src(&compiler->isa, opcode); in is_3src()
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| D | brw_vec4_copy_propagation.cpp | 385 if (inst->is_3src(compiler) && in try_copy_propagate()
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| D | brw_eu_compact.c | 1827 if (is_3src(c->isa, brw_inst_opcode(c->isa, src))) { in try_compact_instruction()
2238 is_3src(c->isa, brw_opcode_decode(c->isa, in uncompact_instruction()
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| D | brw_vec4.cpp | 1700 if (inst->is_3src(compiler) && inst->dst.is_null()) { in fixup_3src_null_dest()
1793 if (inst->is_3src(compiler)) { in convert_to_hw_regs()
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| D | brw_fs_copy_propagation.cpp | 400 if (inst->is_3src(compiler)) { in can_take_stride()
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| D | brw_fs.cpp | 4651 if (inst->conditional_mod && (devinfo->ver < 8 || inst->is_3src(compiler))) in get_fpu_lowered_simd_width()
4659 if (inst->is_3src(compiler) && !devinfo->supports_simd16_3src) in get_fpu_lowered_simd_width()
6258 if (inst->is_3src(compiler) && inst->dst.is_null()) { in fixup_3src_null_dest()
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| D | brw_eu_emit.c | 630 if (is_3src(isa, brw_inst_opcode(isa, insn)) && in brw_inst_set_state()
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