| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 941 int lane_count = LaneCountFromFormat(vform); in pmull2() local
942 for (int i = 0; i < lane_count; i++) { in pmull2()
945 PolynomialMult(src1.Uint(vform_src, lane_count + i), in pmull2()
946 src2.Uint(vform_src, lane_count + i), in pmull2()
1077 int lane_count = LaneCountFromFormat(vform); in bic() local
1078 for (int i = 0; i < lane_count; ++i) { in bic()
1082 for (int i = 0; i < lane_count; ++i) { in bic()
1568 int lane_count = LaneCountFromFormat(vform); in clast() local
1570 ((last_active + offset_from_last_active) + lane_count) % lane_count; in clast()
1595 int lane_count = LaneCountFromFormat(vform); in splice() local
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| D | simulator-aarch64.cc | 497 int lane_count = GetVectorLengthInBytes() / kDRegSizeInBytes; in Simulator() local
501 for (int lane = 0; lane < lane_count; lane++) { in Simulator()
515 int lane_count = GetPredicateLengthInBytes() / kHRegSizeInBytes; in Simulator() local
518 VIXL_ASSERT(lane_count <= UINT8_MAX); in Simulator()
521 for (int lane = 0; lane < lane_count; lane++) { in Simulator()
11046 int lane_count = LaneCountFromFormat(vform); in Simulator() local
11048 for (int i = 0; i < lane_count; i++) { in Simulator()
11084 int lane = reverse ? ((lane_count - 1) - i) : i; in Simulator()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | register-arm64.h | 323 static constexpr VRegister Create(int code, int size, int lane_count = 1) {
324 DCHECK(IsValidLaneCount(lane_count));
326 lane_count);
425 constexpr explicit VRegister(const CPURegister& r, int lane_count) in VRegister() argument
426 : CPURegister(r), lane_count_(lane_count) {} in VRegister()
428 static constexpr bool IsValidLaneCount(int lane_count) { in IsValidLaneCount() argument
429 return base::bits::IsPowerOfTwo(lane_count) && lane_count <= 16; in IsValidLaneCount()
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| /third_party/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 225 uint32_t lane_count = kDRegSizeInBits / kSRegSizeInBits; in GetLane() local
226 VIXL_ASSERT(lane < lane_count); in GetLane()
227 VIXL_ASSERT(GetCode() * lane_count < kNumberOfSRegisters); in GetLane()
228 return SRegister(GetCode() * lane_count + lane); in GetLane()
370 uint32_t lane_count = kQRegSizeInBits / kDRegSizeInBits; in GetDLane() local
371 VIXL_ASSERT(lane < lane_count); in GetDLane()
372 return DRegister(GetCode() * lane_count + lane); in GetDLane()
377 uint32_t lane_count = kQRegSizeInBits / kSRegSizeInBits; in GetSLane() local
378 VIXL_ASSERT(lane < lane_count); in GetSLane()
379 VIXL_ASSERT(GetCode() * lane_count < kNumberOfSRegisters); in GetSLane()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 953 int lane_count = LaneCountFromFormat(vform); in pmull2() local
954 for (int i = 0; i < lane_count; i++) { in pmull2()
956 PolynomialMult(src1.Uint(vform_src, lane_count + i), in pmull2()
957 src2.Uint(vform_src, lane_count + i))); in pmull2()
1935 int lane_count = LaneCountFromFormat(vform); in addlp() local
1936 for (int i = 0; i < lane_count; i++) { in addlp()
1946 for (int i = 0; i < lane_count; ++i) { in addlp()
2087 int lane_count = LaneCountFromFormat(vform); in uxtl2() local
2090 for (int i = 0; i < lane_count; i++) { in uxtl2()
2091 dst.SetUint(vform, i, src.Uint(vform_half, lane_count + i)); in uxtl2()
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| D | simulator-arm64.cc | 1452 int lane_count, int rightmost_lane) { in PrintVRegisterFPHelper() argument
1456 unsigned msb = (lane_count + rightmost_lane) * lane_size_in_bytes; in PrintVRegisterFPHelper()
1465 if ((lane_count == 1) && (rightmost_lane == 0)) { in PrintVRegisterFPHelper()
1480 int leftmost_lane = rightmost_lane + lane_count - 1; in PrintVRegisterFPHelper()
1572 int lane_count = 1 << (reg_size_log2 - lane_size_log2); in PrintVRegister() local
1584 PrintVRegisterFPHelper(code, lane_size, lane_count); in PrintVRegister()
1660 int lane_count = GetPrintRegLaneCount(format); in PrintVWrite() local
1665 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane); in PrintVWrite()
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| D | simulator-arm64.h | 1388 int lane_count = 1, int rightmost_lane = 0);
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| /third_party/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 5652 int lane_count = core.GetSVELaneCount(kBRegSize); in TEST_SVE() local
5653 for (int i = 0; i < lane_count; i++) { in TEST_SVE()
5655 core.zreg_lane(z5.GetCode(), kBRegSize, lane_count - i - 1); in TEST_SVE()
5660 lane_count = core.GetSVELaneCount(kHRegSize); in TEST_SVE()
5661 for (int i = 0; i < lane_count; i++) { in TEST_SVE()
5663 core.zreg_lane(z6.GetCode(), kHRegSize, lane_count - i - 1); in TEST_SVE()
5668 lane_count = core.GetSVELaneCount(kSRegSize); in TEST_SVE()
5669 for (int i = 0; i < lane_count; i++) { in TEST_SVE()
5671 core.zreg_lane(z7.GetCode(), kSRegSize, lane_count - i - 1); in TEST_SVE()
5676 lane_count = core.GetSVELaneCount(kDRegSize); in TEST_SVE()
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| /third_party/node/deps/v8/src/compiler/ |
| D | machine-operator.cc | 1954 #define EXTRACT_LANE_OP(Type, Sign, lane_count) \ argument
1957 DCHECK(0 <= lane_index && lane_index < lane_count); \
1972 #define REPLACE_LANE_OP(Type, lane_count) \ argument
1975 DCHECK(0 <= lane_index && lane_index < lane_count); \
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