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Searched refs:lower_width (Results 1 – 2 of 2) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
Dbrw_fs_generator.cpp620 const unsigned lower_width = in generate_shuffle() local
624 brw_set_default_exec_size(p, cvt(lower_width) - 1); in generate_shuffle()
625 for (unsigned group = 0; group < inst->exec_size; group += lower_width) { in generate_shuffle()
644 if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) { in generate_shuffle()
679 lower_width == dispatch_width; in generate_shuffle()
Dbrw_fs.cpp5286 const unsigned lower_width = get_lowered_simd_width(compiler, inst); in lower_simd_width() local
5288 if (lower_width != inst->exec_size) { in lower_simd_width()
5294 const unsigned max_width = MAX2(inst->exec_size, lower_width); in lower_simd_width()
5302 const unsigned n = DIV_ROUND_UP(inst->exec_size, lower_width); in lower_simd_width()
5361 split_inst.exec_size = lower_width; in lower_simd_width()
5368 const fs_builder lbld = ibld.group(lower_width, i); in lower_simd_width()
5376 split_inst.dst.component_size(lower_width) * dst_size; in lower_simd_width()
6905 const unsigned lower_width = MIN2(dispatch_width, 16); in run_fs() local
6906 for (unsigned i = 0; i < dispatch_width / lower_width; i++) { in run_fs()
6911 .MOV(brw_sample_mask_reg(bld.group(lower_width, i)), in run_fs()