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Searched refs:max_num_temporal_layers (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dradeon_uvd_enc_1_1.c243 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1; in radeon_uvd_enc_layer_control()
247 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); in radeon_uvd_enc_layer_control()
404 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_uvd_enc_nalu_sps_hevc()
414 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_uvd_enc_nalu_sps_hevc()
417 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_uvd_enc_nalu_sps_hevc()
418 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_uvd_enc_nalu_sps_hevc()
562 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_uvd_enc_nalu_vps_hevc()
573 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_uvd_enc_nalu_vps_hevc()
576 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_uvd_enc_nalu_vps_hevc()
577 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_uvd_enc_nalu_vps_hevc()
Dradeon_vcn_enc_2_0.c244 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
259 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc()
262 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc()
263 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
Dradeon_vcn_enc_1_2.c123 enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers; in radeon_enc_layer_control()
127 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); in radeon_enc_layer_control()
300 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, in radeon_enc_nalu_sps()
362 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
372 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc()
375 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc()
376 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
718 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_vps()
729 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_vps()
732 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_vps()
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Dradeon_uvd_enc.h167 uint32_t max_num_temporal_layers; member
Dradeon_vcn_enc.h172 uint32_t max_num_temporal_layers; member