| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface_modifier_test.c | 126 _mesa_sha1_update(&ctx, &surf->meta_offset, sizeof(surf->meta_offset)); in generate_hash()
145 if (surf->meta_offset) { in generate_hash()
175 if (surf->meta_offset) { in generate_hash()
320 assert(surf.meta_offset == expected_offset); in test_modifier()
330 assert(!surf.meta_offset); in test_modifier()
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| D | ac_surface.c | 2510 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0; in ac_compute_surface()
2543 surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2); in ac_compute_surface()
2544 surf->total_size = surf->meta_offset + surf->meta_size; in ac_compute_surface()
2557 surf->meta_offset = 0; in ac_surface_zero_dcc_fields()
2667 if (surf->meta_offset) { in ac_surface_get_bo_metadata()
2668 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset; in ac_surface_get_bo_metadata()
2768 surf->meta_offset = (uint64_t)desc[7] << 8; in ac_surface_set_umd_metadata()
2772 surf->meta_offset = in ac_surface_set_umd_metadata()
2785 surf->meta_offset = in ac_surface_set_umd_metadata()
2817 desc[7] = surf->meta_offset >> 8; in ac_surface_get_umd_metadata()
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| D | ac_surface.h | 379 uint64_t meta_offset; /* DCC or HTILE */ member
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_texture.c | 370 tex->surface.meta_offset && in si_can_disable_dcc()
498 tex->surface.meta_offset = new_tex->surface.meta_offset; in si_reallocate_texture_inplace()
519 assert(!tex->surface.meta_offset); in si_reallocate_texture_inplace()
568 return tex->surface.is_displayable && tex->surface.meta_offset; in si_displayable_dcc_needs_explicit_flush()
725 (usage & PIPE_HANDLE_USAGE_SHADER_WRITE && !tex->is_depth && tex->surface.meta_offset) || in si_texture_get_handle()
737 (tex->cmask_buffer || (!tex->is_depth && tex->surface.meta_offset))) { in si_texture_get_handle()
843 if (tex->is_depth && tex->surface.meta_offset) in si_print_texture_info()
861 if (!tex->is_depth && tex->surface.meta_offset) { in si_print_texture_info()
1065 if (tex->is_depth && tex->surface.meta_offset) { in si_texture_create_object()
1072 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset, in si_texture_create_object()
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| D | si_compute_blit.c | 780 assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX); in si_retile_dcc()
782 assert(tex->surface.display_dcc_offset < tex->surface.meta_offset); in si_retile_dcc()
790 sctx->cs_user_data[0] = tex->surface.meta_offset - tex->surface.display_dcc_offset; in si_retile_dcc()
831 assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX); in gfx9_clear_dcc_msaa()
836 sb.buffer_offset = tex->surface.meta_offset; in gfx9_clear_dcc_msaa()
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| D | si_clear.c | 424 uint64_t dcc_offset = tex->surface.meta_offset; in vi_dcc_get_clear_info()
976 zstex->surface.meta_offset, zstex->surface.meta_size, clear_value); in si_fast_clear()
987 uint64_t htile_offset = zstex->surface.meta_offset; in si_fast_clear()
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| D | si_pipe.h | 1670 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels; in vi_dcc_enabled()
1849 if (!tex->is_depth || !tex->surface.meta_offset) in si_htile_enabled()
1867 assert(!tex->tc_compatible_htile || tex->surface.meta_offset); in vi_tc_compat_htile_enabled()
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| D | si_descriptors.c | 323 meta_va = tex->buffer.gpu_address + tex->surface.meta_offset; in si_set_mutable_tex_desc_fields()
335 meta_va = tex->buffer.gpu_address + tex->surface.meta_offset; in si_set_mutable_tex_desc_fields()
358 if (!tex->is_depth && tex->surface.meta_offset) in si_set_mutable_tex_desc_fields()
408 if (!tex->is_depth && tex->surface.meta_offset) in si_set_mutable_tex_desc_fields()
494 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.meta_offset)); in color_needs_decompression()
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| D | si_sdma_copy_image.c | 202 uint64_t md_address = tiled_address + tiled->surface.meta_offset; in si_sdma_v4_v5_copy_texture()
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| D | si_state.c | 2750 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; in si_init_depth_surface()
2822 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; in si_init_depth_surface()
3281 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; in si_emit_framebuffer_state()
3361 if (!tex->is_depth && tex->surface.meta_offset) in si_emit_framebuffer_state()
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| D | si_blit.c | 1315 if (!tex->surface.meta_offset || !sctx->has_graphics) in si_decompress_dcc()
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| D | radeon_vcn_enc_1_2.c | 1157 if (enc->luma->meta_offset) { in radeon_enc_encode_params()
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| D | radeon_vcn_dec.c | 1927 if (luma->surface.meta_offset) { in rvcn_dec_message_decode()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 438 surf_ws->meta_offset = align64(surf_ws->total_size, 1 << surf_ws->meta_alignment_log2); in radeon_winsys_surface_init()
439 surf_ws->total_size = surf_ws->meta_offset + surf_ws->meta_size; in radeon_winsys_surface_init()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_sdma_copy_image.c | 164 uint64_t md_address = tiled_address + image->planes[0].surface.meta_offset; in radv_sdma_v4_v5_copy_image_to_buffer()
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| D | radv_meta_dcc_retile.c | 222 .offset = image->planes[0].surface.meta_offset, in radv_retile_dcc()
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| D | radv_image.c | 797 meta_va = gpu_address + plane->surface.meta_offset; in si_set_mutable_tex_desc_fields()
805 meta_va = gpu_address + plane->surface.meta_offset; in si_set_mutable_tex_desc_fields()
1219 image->planes[0].surface.meta_offset) { in si_make_texture_descriptor()
1379 (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset); in radv_init_metadata()
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| D | radv_meta_clear.c | 1309 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset; in radv_clear_dcc()
1478 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset + in radv_clear_htile()
1500 uint64_t offset = image->bindings[0].offset + image->planes[0].surface.meta_offset + in radv_clear_htile()
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| D | radv_device.c | 6280 if (surf->meta_offset) in radv_initialise_color_surface()
6331 va += surf->meta_offset; in radv_initialise_color_surface()
6644 surf->meta_offset; in radv_initialise_ds_surface()
6714 surf->meta_offset; in radv_initialise_ds_surface()
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| D | radv_private.h | 2447 image->planes[0].surface.meta_offset; in radv_image_has_dcc()
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| D | radv_cmd_buffer.c | 6420 … uint64_t htile_offset = ds_image->bindings[0].offset + ds_image->planes[0].surface.meta_offset + in radv_cmd_buffer_begin_subpass()
9356 image->planes[0].surface.meta_offset + size, in radv_init_dcc()
9448 image->planes[0].surface.display_dcc_offset != image->planes[0].surface.meta_offset; in radv_image_need_retile()
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